Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

I/O PIN data output delay is so large (cyclone IV)

JJin01
Beginner
1,175 Views
 
0 Kudos
1 Reply
YuanLi_S_Intel
Employee
791 Views
Hi Jongwoo Jin, Apologize that i do not understand the inquiry. The output delay is affected by several factor such as the load Capacitance, trace length and etc. Regards, YL
0 Kudos
Reply