Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19339 Discussions

I/O PIN data output delay is so large (cyclone IV)

JJin01
Beginner
484 Views
 
0 Kudos
1 Reply
YuanLi_S_Intel
Employee
100 Views
Hi Jongwoo Jin, Apologize that i do not understand the inquiry. The output delay is affected by several factor such as the load Capacitance, trace length and etc. Regards, YL
Reply