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I would like to know the assembly tolerance value for PN#10M08SAM153I7G and PN#10M08SAU169I7G.

KLiew7
Beginner
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As I only can found the basic value of package in the datasheet.

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NurAiman_M_Intel
Employee
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Hi,

 

Thank you for contacting Intel Community.

 

Please refer to Packaging specification and dimension page for the device package dimension.

 

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-index/lit-pkg/package.html?family=MAX_10

 

Regards,

Aiman

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RajaSegara_P_Intel
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Hi Aiman,

inside package datasheet only have basic value dont have Assembly tolerance value .

could you please help us out finding the assembly tolerance value?

_RAJA_

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NurAiman_M_Intel
Employee
966 Views

Hi,

 

Kindly clarify what is assembly tolerance that you are referring to?

 

Thank you.

 

Regards,

Aiman

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RajaSegara_P_Intel
966 Views

Hello Aiman,

 

assembly tolerance is package outline tolerance.

In datasheet did not state the package outline tolerance.

we need the value to create footprint for CAD.

 

Thanks

_RAJA_

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NurAiman_M_Intel
Employee
966 Views

Hi Raja,

 

In the below link (Packaging specification and dimension page), Intel did mention the tolerance for the package outline.

Eg: the min and max value stated in the page is the tolerance for the package outline.

 

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-index/lit-pkg/package.html?family=MAX_10

 

Meanwhile,

Sorry to let you know that Intel FPGA do not provide support for PCB footprint symbols for FPGA and CPLD device families, similar to configuration devices.

However, we will continue the support by providing the schematic symbol which you can download from the link above. You could have the schematic symbol in .olb format from the link below:

 

https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/pcb/pcb-cadence.html

 

Thank you.

 

Regards,

Aiman

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