Is it possible to use the FLR for the HIP PCIe AVST core to reset logic?

[JBoot1]

I have an endpoint design which uses the hard IP PCIe avalon-st core with multiple functions. One of the functions is used by a VM so I would like to enable the function level reset for that function. In addition, I would like to be able to reset all the non-core logic associated with that function when the FLR is asserted. However, I don't see a specific port associated with the FLR and the user guide is very sparse when it comes to the FLR. Can the FLR be used to reset logic external to the core? Is there documentation on use of the FLR available?

[SengKok_L_Intel]

Hi,

If you are using PCIe AVST SRIOV IP, then it is possible for the FLR.

Assuming you are using Arria 10 device, you can refer to the link below (section 5.7 & 7.2) for the detail:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_pcie_sriov.pdf

Regards -SK

[JBoot1]

I am using Cyclone V, so the SRIOV is a no go. Is there something similar or at least an application note on accomplishing the same in Cyclone V?

[SengKok_L_Intel]

Hi,

The FLR is not available if this is NOT SRIOV, and I don't see the cyclone V has a similar feature as well. Probably you can create custom logic at the endpoint to perform the reset when receiving certain memory write TLP from the Host.

Regards -SK

[JBoot1]

The document you referenced states that part of the sequence the host writes the FLR bit in the Device Control register. My logic does have access to this register, so I think I can create my logic reset by monitoring that bit. The only question that remains is which bit is it? My references don't specifically define that, nor am I surprised since the PCIe spec doesn't require support of FLR. So I assume Intel has mapped one of the reserved bits in either what they call cfg_dev_ctrl_func<n> or cfg_dev_ctrl2. Does this sound feasible? Can you provide the bit mapping for the control registers?

[SengKok_L_Intel]

The bits that relate to FLR are located at Device capabilities register (bit 28), and Device control register (bit 15) as per the PCIe spec.

In the Cyclone V PCIe AVST user guide, it is mapping to the PCIe Capability Structure (table 8-8), however, the FLR is not supported in Cyclone V PCIe AVST, the IP may not respond with it at all.

Regards -SK

[JBoot1]

If the FLR is not supported in the Cyclone V PCIe AVST, then why are there parameter bits available in Platform Designer to enable it on a per function basis?

[SengKok_L_Intel]

Yes, you are right. I apologize that I was reviewed another user guide and which is not correct. And yes, the Cyclone V PCIe AVST is supporting up to 8 functions, and the FLR option is there.

To initiate the function level reset, it is required to write to Device Control Register [bit 15], and which is mapping to the cfg_dev_ctrl_func<n>[15:0].

Regards -SK