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SK_VA
Beginner
447 Views

IO_OBUF Placement and IC delay in timing path

Is there anyways we can constrain the placement of IO_OBUF so that it is closer to the pad.

 

How can we reduce the IC delay in the timing path?

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17 Replies
KennyT_Intel
Moderator
97 Views

Unfortunately no. What you can do is 1) use fast input and out register. 2) tune the d4 and d5 delay.
SK_VA
Beginner
97 Views

Hi,

Thanks for the reply.

 

Can u please explain more on tuning d4 and d5 delay

KennyT_Intel
Moderator
97 Views

You can go to the chip planner -> locate the IO -> cross probe it to resource property editor.

 

There you can see the delay.

Then, go to settings -> assignment editor -> look for d4 d5 delay and tune accordingly.

SK_VA
Beginner
97 Views

Hi,

 

I am using Cyclone IV with speed grade 8.These options are applicable for all devices and speed grades.Please suggest some document to get more information on these settings.

SK_VA
Beginner
97 Views

Hi,

 

Even after using these options I am seeing the same delay from IO-OBUF to output pin.

 

Regards,

Sanju

KennyT_Intel
Moderator
97 Views

You can attached your project.qar here?

SK_VA
Beginner
97 Views

Hi,

 

Sorry,I cannot share the qar file of the project.

KennyT_Intel
Moderator
97 Views

How about show me the screenshot on where you have set the setting and the resource property editor?

sstrell
Honored Contributor II
97 Views

6.105? Where exactly are you seeing that? That's huge. Can you show your .sdc and the full data path report in that screenshot (Data Arrival and Data Required paths)?

 

#iwork4intel

KennyT_Intel
Moderator
97 Views

You misunderstood how to use the fast input and fast output register. Those have to be points towards the register, base on your screenshot, you have to apply to address_latch. However, even if you apply to it, it will not work because you have a nand_dq_out in btw the IO. I suggest you manually add another register after the nand_dq_out and apply the fast output register.

SK_VA
Beginner
97 Views

Thanks for reply. nand_dq_out is bidirectional.Let me try adding register.

SK_VA
Beginner
97 Views

Hi,

 

I tried this solution by registering the output.But timing is still failing.

KennyT_Intel
Moderator
97 Views

can u send out the same screenshot?

KennyT_Intel
Moderator
97 Views

any update?

SK_VA
Beginner
97 Views

I am still not able to meet the timing with the suggested options.When I add additional registers,the interface itself is not working.

6.105 is not IC delay its cell delay.

KennyT_Intel
Moderator
97 Views

can u share the screenshot?

 

1) the resource property editor that show that the register is inside the DDIO location?

2) Timing analyzer report showing the violation

3) the latest .sdc files showing how frequency that you use for that pin

4) what IO standard that you are using

KennyT_Intel
Moderator
97 Views

Any Update?

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