Is there anyways we can constrain the placement of IO_OBUF so that it is closer to the pad.
How can we reduce the IC delay in the timing path?
You can go to the chip planner -> locate the IO -> cross probe it to resource property editor.
There you can see the delay.
Then, go to settings -> assignment editor -> look for d4 d5 delay and tune accordingly.
I am using Cyclone IV with speed grade 8.These options are applicable for all devices and speed grades.Please suggest some document to get more information on these settings.
6.105? Where exactly are you seeing that? That's huge. Can you show your .sdc and the full data path report in that screenshot (Data Arrival and Data Required paths)?
You misunderstood how to use the fast input and fast output register. Those have to be points towards the register, base on your screenshot, you have to apply to address_latch. However, even if you apply to it, it will not work because you have a nand_dq_out in btw the IO. I suggest you manually add another register after the nand_dq_out and apply the fast output register.
I am still not able to meet the timing with the suggested options.When I add additional registers,the interface itself is not working.
6.105 is not IC delay its cell delay.
can u share the screenshot?
1) the resource property editor that show that the register is inside the DDIO location?
2) Timing analyzer report showing the violation
3) the latest .sdc files showing how frequency that you use for that pin
4) what IO standard that you are using