IO banks voltages

[mnasser431998]

Hello everyone,

I have a simple question about IO banks voltages from PCB design point of view.  I noticed that DDR memories work SSTL IO standard which is about 1.2V and I know that I can change IO standard type in FPGA PinPlanner but how are these voltages generated? do I need to generate them with external supply and connect the bank VCCIO to the supply I need to work with then change the IO standard type within the PinPlanner? or I can hook the VCCIO of all banks to a higher voltage for example 3.3V and then the FPGA internal circuitry takes care of generating the required voltage type? or there are specific voltages I need to connect the FPGA with( ex 3.3, 2.5, 1.2) in order to be able to generate all IO standards?

Thanks in advance

[sstrell · Accepted solution]

You need to follow the pin connection guidelines document for your selected device family, for example Cyclone 10 GX:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-10/pcg-01022.pdf

What's nice about an FPGA is that you can create the design in Quartus, choosing the voltages and standards you need, and the resulting compilation information will help in setting up how to power your device in hardware.