Hello
I'm using the iopll IP core on my Arria10 FPGA HW.
I observe that the output clock generated is getting disturbed with respect to temperature variations - to be specific, the output clock is more stable when the device is hot and highly instable when the device gets colder.
Is this a known issue on the FPGA HW or the IP core.? Is there a fix to it.?
I've attached a screenshot of the output clock probed on the oscilloscope.
But we also notice that the status of 'locked' pin of the iopll remains unchanged despite the instability at the output clock.
Please let us know your feedback for the same.
