We are using MAX 10 FPGA "10M40DAF484C7G" device in our project. Chip select for the Board management controller(AST 2600) is routed through this device which connects to the flash. As a result BMC is getting corrupted most of the times during FPGA programming. We have tried ISP clamp feature to avoid the corruption and the below is our observations.
We would like to know if there is any way to drive the CS low only during the CFM is loaded to SRAM, Not once the programming is initiated. And is there any other feature which we can use to avoid this corruption.
Any suggestions are much appreciated
Thanks and Regards
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Intel Server Specialist
I believe that the "CS" pin that is used to connect to the FLASH is actually a GPIO on MAX 10. So your concern is how to make it low during programming and in user mode?