Implementing custom DDR controller in Cyclone SOC

[Altera_Forum]

Hi, 

I understand that there are external DDR memory devices attached to HPS and FPGA section in Cyclone SOC. Is it possible to have my own DDR controller in the FPGA section and use the DDR PHY generated by ALTMEMPHY to access the DDR memory connected to FPGA section? If this is possible, please suggest appropriate development board. Thanks.

[Altera_Forum]

Hi, 

 I don't have any direct experience with this but based on this document www.altera.com/literature/wp/wp-01188-hard-memory-controller-cv.pdf it seems like it is possible. Specifically it states that the memory controller can be bypassed (Bottom of page 2). I would probably confirm this with Altera though.   The Altera Cyclone V SOC Development Kit would be a good board to try this on since it has dedicated DDR3 for the FPGA as well as a hard memory controller and phy for the FPGA.

[Altera_Forum]

--- Quote Start ---  Hi,  I don't have any direct experience with this but based on this document www.altera.com/literature/wp/wp-01188-hard-memory-controller-cv.pdf (http://www.altera.com/literature/wp/wp-01188-hard-memory-controller-cv.pdf) it seems like it is possible. Specifically it states that the memory controller can be bypassed (Bottom of page 2). I would probably confirm this with Altera though.   The Altera Cyclone V SOC Development Kit would be a good board to try this on since it has dedicated DDR3 for the FPGA as well as a hard memory controller and phy for the FPGA.  --- Quote End ---   _____________________  Thanks for the response. The white paper that you suggested is on cyclone V FPGA series not on cyclone V SoC FPGA series. I want the ARM cores interfaced with my custom DDR controller thru AXI and DDR talking to external DDR via DDR PHY. Do you feel this is achievable with cyclone V SX SoC FPGA kit? Please suggest me some tutorials on SoC design using ARM cores. I am finding it tough to get any tutorial unlike Xilinx :(

[Altera_Forum]

The controller and PHY are both harden silicon inside the HPS block and the PHY interface cannot be exposed to the FPGA in order to add your own controller. The closest you can get to what you were asking about is to instantiate the memory controller in the FPGA fabric and then connect it to the HPS-to-FPGA bridge, but you'll probably take a performance hit by doing that.

[Altera_Forum]

Sorry I did not see that the white paper was for the FPGA not the SOC version. You definitely can't replace the dedicated HPS hardened memory controller. But some models of the Cyclone V SOC models have one or more hardened memory controller with phy to the FPGA. Shouldn't it be possible to use a customized soft memory controller with one of the hardened phys dedicated to the FPGA as described in the Cyclone V white paper I linked to? 

 If that is possible then you can connect your custom memory controller to the HPS via the h2f_axi_master as you said BadOmen. This can be up to a 128-bit interface compared to 64-bit for HPS to Hardened DDR controller. The maximum frequency is probably less. But I would expect you could get decent performance.

[Altera_Forum]

Regarding tutorials. The only ones I know of are www.rocketboards.org.

[Altera_Forum]

Thanks for all the answers. I have cyclone V SoCKit for which I do not have the CD which contains example designs. If anyone has those contents, please share it with me. 

Thanks.

[Altera_Forum]

Look here for Cyclone V SoCKit resources http://www.rocketboards.org/foswiki/documentation/arrowsockitevaluationboard

[Altera_Forum]

Is that the development board you have? There are a few of them and that particular one is the Arrow dev kit. Judging by the block diagram it has a similar memory setup as the Altera dev kit that I'm more familiar with. 

 The SDRAM interface connected to the FPGA side of the device should support connecting a custom SDRAM controller to the PHY but I'm not sure if that's what you are looking for. Also I don't think you can use ALTMEMPHY with Cyclone V devices, I think you can only use UniPHY on newer FPGAs/SoCs.