Hi Elea,
You are correct that FLASH_WE is the Write Enable for the flash device. This signal is asserted when performing a write operation to the flash.
FLASH_OE is the Output Enable signal. This has to be asserted when performing a read operation. When it is negated, the data I/O pins of the flash are put into a high impedance state.
Both of these signals may be shared with other devices on a common address/data bus, and this is where the third signal, FLASH_CE, comes in. This is the Chip Enable, and the flash device only responds to the signals on the WE/OE lines when its own CE is asserted. Each device on a shared bus will have its own Chip Enable signal.
You will find similar signals on other memory devices such as RAMs. On some devices the WE and OE signals are replaced by a single R/W input (which signals a Read when high and a Write when low). Chip Enable is sometimes called Chip Select (CS).
Have a look at the datasheet for your flash device and you will see timing diagrams showing how these various signals are used in conjunction with the address and data buses to perform reads and writes (possibily in several different ways).
I hope this answers your question.
Cheers
Sharkybaba
