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I have relatively complex circuit involving adders and cascaded embedded multipliers.

I was assuming that it would be enough to wait for 4 clock cycles between loading data into the multiplier and getting output from it, but I was mistaken.

I can increase delay, but it will not guarantee that in the next builds fitter put the logic the way that 5 or 6 cycles will not cause the problem.

Therefore there's a need to tell Quartus to make *predictable* layout for the circuit.

Please advise how to do it properly. I need adders with respective registers to be close to embedded multipliers, and 9x9 multipliers to be selected as close as possible to each other for cascading.

Thank you.

P.S. Ideally I will be super grateful if you can explain how to actually predict the timing, or where in Quartus I can see it in then comprehensive way.

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You may take a look in multicycle:

https://community.intel.com/t5/FPGA-Wiki/Timing-Constraints/ta-p/735562 ->

**Understanding start/end setup/hold multicycle constraints**

Or, this document: https://www.intel.com/content/dam/altera-www/global/en_US/uploads/3/3f/TimeQuest_User_Guide.pdf

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Thank you. Not sure I can write anything useful into SDC file immediately using these guides, however the matters are more or less clear. The TimeQuest analyzes the already fitted and assembled design for timing violations. I ask to instruct fitter upfront to place stuff the way they it does not violate the timing.

My case is super simple. Let;s imagine I have the following circuit:

*properly*instruct software to fix the timing in design.

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I believe this training talks a bit about multicycle, along with the other required constraints, like clock constraints:

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1118.html

The cycle count seems to be the most important thing here, so I'd recommend adding pipeline registers instead of relying on multicycle and the Fitter routing appropriately.

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1. What should I write to instruct fitter/assembler to lay cascaded embedded multiplier and accumulator out to be ready with math within, let's say, 3 cycles for further latching?

You may use the multy cycle in the SDC, I suppose you cannot add pipeline register?

Multi Cycle is not hard to understand, If you find difficulty to understand this, we can setup a call for you.

2. Is there any way to force Quartus to re-fit, or give hard error, if it can not lay out the circuit the way to satisfy the multicycle timing requirement?

Unfortunately, nope. But you can analyze the Timing analyzer waveforms. Once you had set the multicycle, the result will be reflected in timing analyzer

3. If I have tons of warnings in the TimeQuest analysis, how do I find the ones I really care about? (^F does not work in the "Compilation report" window).

You can suppress the warning message, https://www.youtube.com/watch?v=NHsprt0UKEw

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Any further queries?

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Hello Kenny, yes. Would it be possible to send you (or any other knowledgeable and experienced person you appoint) email with details on the design and description of the problems I have.

I have recently did several changes, putting output registers to the pin nearby cells, and it was working for a while, but as design grows this is not enough and workaround does not work any more.

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Sure. you may check your email on this

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Is there any update?

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Hi Eugeny,

Can you check your email? there are some update question over there.

Thanks

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*We do not receive any response from you to the previous reply that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. *

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