Intel Cyclone 10 GX EMIF IP timing model required for DDR3 SI simulation

[Avinash_B_P]

Hello 

I am running the ddrx simulation wizard with hyperlynx tool. i am DQ (data) lines are failing with setup and hold time at slow swing. for this error i wanted to run the wizard with adding timing model manually. please help me to get the timing model data. please refer the attached for required data info.  

Regards 

Avinash B P

[Avinash_B_P]

DQ (data) lines are failing with setup and hold time at slow swing at read cycle. write cycle is good. 

[yoichiK_intel]

Hello 

Timing analysis will be analyzed in the Quartus Timing Analysis.  There is DDR report tab in the Timing Analysis.  User only need to check the Signal Integrity of each signals by SI simulation.

[Esteban_D_Intel]

Hello Avinash_B_P, 

Thank you for posting on the Intel® communities.

Based on your product Intel® Cyclone® 10 GX,

We would like to inform you that we have a forum for those specific issues and products, so we are moving it to the appropriate support so you can get answered more quickly. 

https://community.intel.com/t5/Programmable-Devices/bd-p/programmable-devices 

Esteban D.  

Intel Technical Support Technician