It looks like the TDI and TMS are internally pulled up to VCCIO (3.3V), but when we want to flash the FPGA through intel download cable, the voltage levels are all at 2.5V. This will cause a conflict in voltage levels? Is there a way to disable the internal pull ups on these 2 lines?
You can't disable the internal weak pullup. You can change the VCCIO of the IO bank or change VCC of the JTAG signal.
Side notes: There will be no contention between 3.3V and 2.5V as the Vih/Vil is the same.
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