Intel Max 10 FPGA VCC and GND short after few days

[Muralidharan]

Hi, Greetings! History: We are using Intel 10M25SAE144I7G FPGA in the design. Rev1 Board is working fine, in the Rev 2 Board we used the same FPGA design code and some of the pins assigned as input/ output in Rev1 is unused and left floating in Rev2. There is no other difference I could see between Rev1 and Rev2 Board. Issue: Initially the design was working fine and after few days of use, Sudden heat observed, and the FPGA chip failed and the Vcc and Gnd pins are shorted when measured. Power Supply Details: Main Power is 24 DC to the Board and then it is converted to 12VDC by Murata DC-DC module and then using two LDO'S to convert from 12V to 5V DC and from 5VDC to 3.3V DC. The FPGA is powered with 3.3V LDO. Query: 1.If we defined the pins in platform designer and if we left it floating any issue can occur? 2. One more suspect is on the ESD. Please support! I can share the pin assignment details if required.

[Farabi]

Hello,

1. Are you able to do the IV curve?
2. how many units observed the same?
3. can you snapshot the top marking of the fail unit?
4. Do you want to send the unit for FA?

regards,

Farabi

[Muralidharan]

Hi Farabi,

Thanks for your response!

1. I biased at 1.8V and gradually increased the current till 1A during my debug and observed FPGA heats more than 80 degress, disconnected the power immediately and I haven't done further testing.

2. 4 units at different intervals. Initially it works after continuous usage, it experiences sudden heat and fails!

3. Sure, I'll share by Monday.

4. Currently it is on the board, I need to desolder. I'll update you later on the shipment for FA. Yes, I can send if needed.

5. Any suggestion, what are the possible causes for FPGA failure? I have put design release on hold because of this failure!

[Zawani_M_Intel]

Hi Muralidharan,

It is best to tie a non-driven input to something (eg. GND or VCC) instead of leaving it floating to prevent inadvertent toggling.  

A non-driven input could toggle from board noise and such and draw unwanted current.

If you have unused general purpose IO that do not have a signal assigned to it, it’s also a good idea to have it basically tied to some know value (eg. GND or VCC).  

Quartus has the option to set unused IO as an output driving GND or an input with weak pull-up.  

Yes, the idea is to prevent inadvertent toggle and thus unwanted current draw.

If the worst scenarios happened, it is possible enough signals and current going into a pin and can damage the pin.

From now you will observed sudden heat, pin shorted to GND and even the device death.

This is Electrical Overstress phenomenon.

Regards,

Wani

[Muralidharan]

Hi Wani,

Thanks for your Feedback!

Non- Driven input pin, I'll connect to GND.

What about Non-Driven Output pin? Any suggestion here?

Attached the input and output pin details which is defined in the FPGA Pin Planner for Rev1 Board and unused in Rev2 Board and left floating.

We are using the same FPGA design files in both of our custom board Rev1 and Rev2.

Thanks,

Muralidharan G

[Zawani_M_Intel]

Dear Muralidharan,

I hope I answer your questions.

Is there anything we can help with?

Wani

[Muralidharan]

Hi Wani,

I have replied in your previous feedback dated 10-18-2023, please check.

Thanks,

Muralidharan G

[Zawani_M_Intel]

Hi Muralidharan,

Noted, please allow me some time to look into it. I will reply you back shortly.

Wani

[Muralidharan]

Hi Wani,
Any update?
Waiting for your reply for the floating output pins.

Thanks,
Muralidharan G

[Zawani_M_Intel]

Hi Muralidharan,

Hope that my answer can help you.

We recommend to connect non-driven output pin to be connected to GND. You can set the pin to GND by using Quartus. Physical connection is not needed as the connection is already exist in FPGA package.

Thank you!

Wani