Invalid output from MM--> ST (SGDMA)

[Altera_Forum]

Hi, 

  Im wondering if anyone experience this problem before. i was transferring content in my SDRAM to a DCFIFO outside of SOPC using SGDMA. The SDRAM content is all zeros. but after the SGDMA transfer, i can see 1 in the upper bytes, and 0 in the lower bytes as shown in the attached picture.   The FF in the first 2 byte is correct, that is not the problem.   Michael

[Altera_Forum]

No I haven't faced a problem like that... Are you sure that the RAM contents is 0? Especially if you have a data cache, ensure that it is flushed before you start the transfer. 

Is the DMA reading at the correct address? Use a Signaltap instance to monitor what the SGDMA is doing.

[Altera_Forum]

The problem was solved.. it turns out to be a "loose" wire between FPGA and acq board that is causing this problem.