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Also, is the "high performance controller ii" a "hard memory controller"? I find the reference manual somewhat confusing!
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It depends on your target device family. Cyclone V and Arria V, I believe, were the first to have hard memory blocks (hard PHY with soft controller). Arria 10 and Stratix 10 have hardened PHY and controller.
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What is the difference between "hard" and "hardened" in Altera-speak? In programming, "hardened" usually has to do with security and/or fault- or interference-tolerance.
Does "hardened" in an FPGA feature mean that it's "partly ASIC'ed"?- Mark as New
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Hard or hardened means the same thing. It means that it is a fixed structure in the device, like an ASIC as you mention. Even hard IP, though, does have some customization usually possible.
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