JTAG chain broken after FPGA configuration

[Shihang]

Hi there,

I am using an Agilex 7 I-series Development Kit (DK-DEV-AGI027R1BES, AGIB027R29A1E2VR3), and Quartus 24.1 on Linux.

After programming the device with a CXL Type 3 Example Design and restarting the server, the FPGA's JTAG chain is no longer operational. When I run `jtagconfig --debug`, I see:

```

1) AGI FPGA Development Kit [1-1]
(JTAG Server Version 24.1.0 Build 115 03/21/2024 SC Pro Edition)
Unable to read device chain - JTAG chain broken

Captured DR after reset = ()
Captured IR after reset = ()
Captured Bypass after reset = ()
Captured Bypass chain = ()
JTAG clock speed auto-adjustment is enabled. To disable, set JtagClockAutoAdjust parameter to 0
JTAG clock speed 24 MHz

```

I used `quartus_pgm` to program the FPGA (configuration file passed via `-c`, copied below). This should use the on-board USB blaster, as opposed to an external blaster. These steps worked well in an internal project built on top of the Type 3 example design. However, when I used this config on a newly generated Type 3 example design project and ran it, the JTAG issue occurred.

```

/* Quartus Prime Version 24.1.0 Build 115 03/21/2024 SC Pro Edition */

JedecChain;

FileRevision(JESD32A);

DefaultMfr(6E);

P ActionCode(Ign)

Device PartName(AGIB027R29A) MfrSpec(OpMask(0));

P ActionCode(Ign)

Device PartName(1_BIT_TAP) MfrSpec(OpMask(0));

P ActionCode(Ign)

Device PartName(10M50DAF256) MfrSpec(OpMask(0) SEC_Device(QSPI_2GB) Child_OpMask(3 1 1 1) PFLPath("./intel_rtile_cxl_top_0_ed/hardware_test_design/output_file.pof"));

ChainEnd;

AlteraBegin;

ChainType(JTAG);

Frequency(16000000);

AlteraEnd;

```

Thanks in advance for your help.

[zutalors]

Does it work if you use the factory_recovery/fpga_recovery/AVSTX8.pof for you dev kit? If it works with the recovery pof then it might be that your pof build have some issues. Does it also happen if you load the sof you used to create the pof? There's also a PCIe reference design in examples/pcie_ed/pcie_ed/output_files/convert-to-pof/output_file.pof which you might try.

[Shihang]

Thanks for your reply! I have tried the factory recovery approach: this results in a "Flash Loader IP not loaded on device 2" error on Quartus. While I've seen this error on the forum, I wasn't able to find any post that was similar to my situation and/or had fixes that worked on my end.

[zutalors]

Device 2 is the MAX unless the JTAG chain has been modified by DIP switch settings, which you might want to check. But it sounds like it's not able to find the indirect programming logic in the MAX.

At least for the dk-dev-agi027-ra version of the board there's a pof and readme file in factory_recovery/max10_recovery. This might be a thing to try if you're out of luck at all other ends.

[Fakhrul]

Hi Shihang,

Any updates? Please feel free to reach out if there's anything you'd like us to assist you with. If we do not receive any updates from you soon, this thread will be marked as inactive and transitioned to community support.

Thank you for your understanding.

Best regards,

Fakhrul

[Shihang · Accepted solution]

We were able to restore the JTAG chain by switching SW8.2, which disables the FPGA on the JTAG chain. Once we do that, we were able to restore the max10 device using the factory recovery steps as described in the files that came with the board.

[Fakhrul]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.