Jtag Problem

[Altera_Forum]

Hello everybody, 

 i have big problem, i use CIII FPGA on my own board (EP3C16Q240). I try use USB BLASTER (Rev. B), but this is response:  Error: Can't access JTAG chain Error: Operation failed.  Anyway, if i use ByteBlasterII(LPT1), so JTAG works correctly. But i need use Usb Blaster, because i wanna use Nios II in CIII, but Nios II IDE and ByteBlaster are not friends and i can not download software to Nios II(if i use for FPGA programing ByteBlasterII).  In pdf file is schematic of my board.  Please, do you know where is mistake? what is problem? i am confuse now, because FPGA is ok.  Thank you for your answer, Vasek(Morrpheus)  PS: Vccio = 3.3V Vcca = 2.5V(for PLL) Vccint = 1.2V

[Altera_Forum]

JTAG Connector and pull/downs are okay 

 M25P40 DATA0 needs the 25Ohm as mentioned in C3 PDF.  If your byteblaster handles the pcb correctly and the usb blaster does not, then 2 possibile reasons can be.  1. check your usb blaster, try to change the yellow flat cable to a normal ribbon type (like your harddisk cable inside your pc) and make this cable as short as possible (5cm) some usb blaster Rev.b we hav had these problems  2. check your pcb for trace length, i remember a pdf teling max trace length for the jtag signals. again make these traces as short as possible   what messages do you get when starting jtagconfig.exe ?  how is your layerstackup ?  be aware of the 3,3V theme about Cyclone III devices, we moved to 3,0V because of that.

[Altera_Forum]

1 - I would of course check with another USB blaster just to make sure your Blaster doesn't have some issue. 

 2 - If you have an oscilloscope at your disposal you should take a look at the JTAG signals on the board just so you can understand what's going on.  3 - If the USB-Blaster is working properly my first suspicion is that you are right on a timing edge that the USB-Blaster is unable to resolve. Here are some things you could try:  a - Try adding some capacitance to the JTAG traces while you try to scan the chain. Like holding a screwdriver tip on the clock line or data line. Sometimes this added drag on the signal can be enough to push things into a working condition.   b - Add a small series resistor into the TDO trace, TCK trace, or TDI trace.  c - Try adding a bit of cable between the USB Blaster and the JTAG header on your board.  Can you describe your JTAG topology?  Jake

[Altera_Forum]

I believe your pull up voltage for the jtag pin 5 and 9 have to be the same as VCCIO 3.3V.

[Altera_Forum]

no for cyclone III 2,5V ist correct, see altera cIII documentation 

http://www.altera.com/literature/hb/cyc3/cyc3_ciii51010.pdf Figure 10–24 this works perfectly for my EP3C40 designs.

[Altera_Forum]

1. Recent Quartus versions have a JTAG Chain Debugger included with the programmer tool, that can help to detect hardware problems.  

 2. The most serious problem with the Rev. B JTAG flex print is, that it can break rather easily. A short IDC cable can replace it without problems.  3. The JTAG interface isn't very sensitive to signal quality issues. Basically, TCK is the only signal that can cause transmission errors due to excessive ringing on bad designed boards, all other signals are only sampled at TCK edges.