LPM_MULT not working for Cyclone 10 GX device

[K_Crocker]

I can't get a simple LPM_MULT instantiation to work. It simulates fine in Questa, synthesizes in Quartus Prime 24.2.0 Build 40 06/27/2024 SC Pro Edition without warnings, but 'result' is always 0 with 'dataa' of 8333 and 'datab' of 100. The FPGA family is Cyclone 10 GX. I can post additional code and a screenshot of the SignalTap upon request:

component mul_18bit_7bit is
   port (
      dataa : in std_logic_vector (17 downto 0) := (others => 'X');
      result : out std_logic_vector (24 downto 0);
      datab : in std_logic_vector (6 downto 0) := (others => 'X');
      clock : in std_logic := 'X'
   );
end component mul_18bit_7bit;

Component is pipelined with one clock, unsigned. I've tried adding synchronous and asynchronous resets. 'datab' is a constant in this case, and I've tried instantiations where I specify 'datab' as a constant. 'clock' is a free-running at 100 MHz. All attempts yield a 0 'result'.

Any ideas would be greatly appreciated!

[ShengN_Intel]

Hi,

Are you use LPM_MULT instantiation? If yes, can you try with the LPM_MULT from ip catalog? Probably some setting is not allowed.

Thanks,

Regards,

Sheng

[umit-sami]

It might be a clocking problem.  Your multiplier won't produce valid output (that's why you are getting zero) until a valid input is provided after the rising clock edge. If clock is not configured or not routing it won't work.  In your code you have clock set to X which is not accurate. X is the default value for "simulations" only. Be sure your clock is wired and hits the LUT blocks. Also you may want to tap/monitor the clock signal with SignalTap for verification ! Good luck and have lots of fun debugging your code

[umit-sami]

clock : in std_logic := 'X'  what is your clock speed ? 100 Mhz ?

[K_Crocker]

Here is a screenshot of the Signal Tap instantiation. The 'toggle_h' signal is a D-type flip-flop toggled at 100 MHz. Signal 'act_frame_time_h' is 'dataa' of the LPM_MULT instantiation. Signal 'act_frame_clocks_h' is the 'result'. Signal 'datab' is 'clks_per_us_h' defined as follows:

constant clks_per_us : natural := 100;
constant clks_per_us_h : std_logic_vector (6 downto 0) := conv_std_logic_vector (clks_per_us, 7);

The 'X' you refer to is part of the instantiation declaration and is superseded by the argument 'clk_r' which is the 100 MHz clock associated with the parameter 'clock'.

[K_Crocker]

Yes. I created an instantiation with the IP catalog:

General tabGeneral 2 tabPipelining tab

[ShengN_Intel]

Hi,

Possible to provide your design for taking a look?

Thanks,

Regards,

Sheng

[K_Crocker · Accepted solution]

I could strip down the design, but I have some new information. I was able to work around the issue by changing the implementation style to "Use logic elements", in lieu of "Use the default implementation" or "Use the dedicated multiplier circuitry". I believe the default implementation is to use the dedicated multiplier circuitry. I think there really is a bug in the Altera LPM_MULT IP when using multiplier blocks.

Changed to "Use loigc elements"Signal Tap showing ckt works as expected

[ShengN_Intel]

Hi,

I use the setting mentioned and tap the LPM_MULT IP standalone and get the correct result (attached screenshot).

Do you get any problem tap the LPM_MULT standalone?

May be try to clean the project and re-generate the IP.

Thanks,

Regards,

Sheng

[K_Crocker]

What does "tap the LPM_MULT standalone" mean? What version of Quartus Pro are you using? What is the FPGA you are using?

[ShengN_Intel]

Hi,

I mean just give a wrapper to LPM_MULT and assign value to dataa and datab. Version 24.3 and Arria 10 device (currently don't have cyclone 10 gx available). I don't think device will matter.

Thanks,

Regards,

Sheng

[K_Crocker]

I'm not sure what the point is. The wrapper was created by the wizard. Is the following incorrect? (Note, this is for the workaround version using logic cells. The lpm_hint in the broken version was just "MAXIMIZE_SPEED=5").

---

// mul_11bit_14bit.v

// Generated using ACDS version 24.2 40

`timescale 1 ps / 1 ps
module mul_11bit_14bit (
input wire [10:0] dataa, // dataa.dataa, Input data A of this multiplier
output wire [24:0] result, // result.result, Result of the multiplier
input wire [13:0] datab, // datab.datab, Input data B of this multiplier
input wire clock // clock.clk, Clock input for pipelined usage.
);

mul_11bit_14bit_lpm_mult_1921_acrkt5q lpm_mult_0 (
.dataa (dataa), // input, width = 11, dataa.dataa
.result (result), // output, width = 25, result.result
.datab (datab), // input, width = 14, datab.datab
.clock (clock) // input, width = 1, clock.clk
);

endmodule

---

---

module mul_11bit_14bit_lpm_mult_1921_acrkt5q (
clock,
dataa,
datab,
result);

input clock;
input [10:0] dataa;
input [13:0] datab;
output [24:0] result;

wire [24:0] sub_wire0;
wire [24:0] result = sub_wire0[24:0];

lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "UNSIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 11,
lpm_mult_component.lpm_widthb = 14,
lpm_mult_component.lpm_widthp = 25;

endmodule

---

[ShengN_Intel]

Hi,

Yes, then reg the dataa and datab with values for example:

module lpm_mult_driver (

  input wire clock,

  output wire [24:0] result  

);

  reg [10:0] dataa;

  reg [13:0] datab;

  mult mult_inst (

    .dataa(dataa),

    .datab(datab),

    .clock(clock),

    .result(result)

  );

  always @(posedge clock) begin

    dataa <= 11'd833;

    datab <= 14'd100;

  end

endmodule

Does tap the LPM_MULT standalone okay? I don't have any issue.

Thanks,

Regards,

Sheng

[K_Crocker]

dataa and datab are written to once and are static, so registering them shouldn't have an effect.

[ShengN_Intel]

Hi,

So you able to tap correctly with just LPM_MULT IP?

Thanks,

Regards,

Sheng

[K_Crocker]

If lpm.hint is "DEDICATED_MULTIPLIER_CIRCUITRY=NO,MAXIMIZE_SPEED=5" multiplier operates nominally.

If lpm.hint is "MAXIMIZE_SPEED=5" multiplier always outputs 0 for my FPGA (10CX150YF780E6G).

[ShengN_Intel]

Hi,

May I know whether you tap the IP standalone?

Thanks,

Regards,

Sheng

[K_Crocker]

No. We've visited this issue before. The IP wizard instantiates lpm_mult. I've shown you the code it created. I don't see the point of doing this standalone. Perhaps you can tell me why a standalone instantiation would be any different from the IP wizard instantiation. The IP wizard creates a wrapper. I would just be removing the wrapper.

[ShengN_Intel]

Hi,

Since I can't duplicate the problem with standalone LPM_MULT IP, so possibly provide your sample design for checking?

Thanks,

Regards,

Sheng

[K_Crocker]

I can no longer replicate the issue either. I tried creating a minimal project with two multipliers, one using hardware multipliers and one using logic elements. The results were identical.

Then, since I use 3 instances in my full design, I used one with hardware multipliers and two with logic elements. The results were identical.

So, for now, let's assume the problem is solved (at least until it fails again)!

Thank you for your help!