I am trying to transmit data from STRATIX v DEVELOPMENT board (5SGSMD5K2F40C2) to STRATIX IV DEVELOPMENT BOARD (EP4SGX230KF40C2) through LVDS DPA mode using HSMC connector, I observed the following through signal tap.
1.Data is transmitted properly from STRATIX V FPGA.(at the 8b/10b encoder input).
2.But at the receiver i.e STRATIX IV FPGA, the data is getting corrupted( at the 8b/10b decoder output).
3.I had the following critical warning while generating .sof file of STRATIX IV FPGA.
--placement of some of the LVDS pins relating to instance <> may not comply to the existing ALTLVDS DPA mode pin restriction guidelines.
Please help, Thank you.
