LVDS standard for PCIe Reference Clock pins

[Altera_Forum]

Hi, 

I am trying to connect my Cyclone IVGX FPGA (EP4CGX150CF23C7) with a TI multicore DSP via PCIe protocol using PCIe hard IP.  According to cycloneIV handbook, the refernce clock pin standard is HCSL with differential dc coupling.   1) Can I use LVDS protocol with differential AC Coupling as shown in fig 1-27,28 in cyclone IV handbook volume 2?  2) Also, I am unable to find the voltage levels for HCSL standard. Any help?  Thank you all for your time and effort.   Regards.

[Altera_Forum]

--- Quote Start ---  Hi, I am trying to connect my Cyclone IVGX FPGA (EP4CGX150CF23C7) with a TI multicore DSP via PCIe protocol using PCIe hard IP.  According to cycloneIV handbook, the refernce clock pin standard is HCSL with differential dc coupling.   1) Can I use LVDS protocol with differential AC Coupling as shown in fig 1-27,28 in cyclone IV handbook volume 2?  2) Also, I am unable to find the voltage levels for HCSL standard. Any help?  Thank you all for your time and effort.   Regards.  --- Quote End ---    Hi, Did you find out if you can use LVDS for PCIe reference clocks. I'm having same trouble now and Alteras documentation does not give a clear answer. Please let me know if you found out something.  -kramu