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LVDS

MK_ABQ
New Contributor II
1,490 Views

Hi,

I am using Intel Arria 10 GX FPGA development kit. 

DK-DEV-10AX115S-A

The development kit has two FMC connectors FMC A and FMC B. There are LVDS standard pins in the connector. 

 

I am trying to use three pins from FMC B.

My design is simple. I am just driving the three pins with hard coded 1 and 0, and configured as LVDS standard in the qsf. 

pin 1 <= '1';

pin 2 <= '0';

pin 3 <= '0';

 

just few lines of code and no LVDS IP used. I believe this is enough to see something from the connector, but when I probe with scope  I see that all three pins are just showing 1.8V. Am I missing something?

 

Thanks,

MK

 

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FvM
Valued Contributor III
1,408 Views

You don't need to connect differential termination to see specified LVDS voltage range. Unterminated pins simply swing to VCCIO and GND for 1 and 0 state. In so far termination isn't required to see LVDS output working. There must be another elementary problem in your test, e.g. probing wrong FMC pins.

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7 Replies
FvM
Valued Contributor III
1,487 Views
Hi,
your setup isn't clear. If you chose LVDS IO standard, a pin pair is used. So how do you measure three pins? There 6 pins involved with 3 LVDS outputs.
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MK_ABQ
New Contributor II
1,479 Views

Hi,

Lets take just one pin for example. Pin 1 refers to an LVDS pin, and yes both P and N of this pin is defined in QSF. My question is, lets say if I drive the LVDS pin as "logic 0" or "logic 1" or say I just toggle 1 and 0 in regular interval, I expect it to show in the acutal hardware when I probe.

I am wondering if just declaring the signal as an output port in VHDL, and assigning the correct pin in qsf is just enough for LVDS?. or I should use any intel IP which has configurations to be able for the signal to propogate in LVDS pin. 

 

Thanks

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FvM
Valued Contributor III
1,462 Views

Hi,
check in the Quartus .pin file which pi s have been actually assigned.

The general way is to use a single port pin in top level entity, assign the positive pin of an available pin pair to it in pin planner or assignment editor and specify LVDS IO standard. The negative pin will be assigned automatically, both pins are shown in pin planner.

MK_ABQ
New Contributor II
1,443 Views

Hi,

Yes I double checked quartus pin planner and also fitter report and the pins looks okay and have been assigned correctly, but I am not able to see anything in the LVDS pin. 

So, I don't need an LVDS IP ?

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_AK6DN_
Valued Contributor I
1,422 Views

LVDS (low voltage differential signaling) is normally implemented as a current source/sink between the P and N driver.

So you need a (typical) 100ohm differential load at the receiver, and measure the voltage across that.

So put 100ohms between your P and N outputs and measure the differential voltage across that as you drive a '1' and '0' internally.

Measuring the unloaded driver pins is not generally meaningful as no current can flow thru an effective infinite load resistance.

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FvM
Valued Contributor III
1,409 Views

You don't need to connect differential termination to see specified LVDS voltage range. Unterminated pins simply swing to VCCIO and GND for 1 and 0 state. In so far termination isn't required to see LVDS output working. There must be another elementary problem in your test, e.g. probing wrong FMC pins.

AqidAyman_Intel
Employee
1,241 Views

Hi,


I seen that you accepted the answer as solution. I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



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