Load pcie design without reboot

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Load pcie design without reboot

892 Views

Hi,

The question has probably come up in previous threads but I haven't found yet so I post the question myself. If I missed the related thread please give me the url. Thanks.

I've got a pcie design on a stratix IV. I've noticed that with some servers (usually high-end servers: IBM, Dell, HP, etc.) reloading the firmware into the FPGA while server runs make the motherboard sends a unknown NMI to the CPU. Sometimes this scenario crashes the server or reboot it.

I wanted to know if anyone went to this issue and solved it.

Thanks.

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.