Looking for FPGA that can have FF and shift register that can clock at 1GHz

[Altera_Forum]

Hi 

I designed with Apex 10 years ago. I am designing circuit that use FF, latches, 14 bit adders, and some simple combination logic that can run on a synchronous 1GHz clock. I don't need any fancy processor, DSP etc, just simple circuit even the old MAX Plus can do, but just need to run at 1GHz clocking.  Can you suggest the fastest and latest family FPGA I can look into?  I programmed with the Quartus 10 years ago, what is the latest version for programming? Is it similar with the original Quartus I learned before?  Is there any free simulation program?  Thanks  Alan

[Altera_Forum]

Although FPGA's have improved greatly since 2005, 1 GHz is still pushing the edge. 

 Is the data coming in on SERDIES?  Right now Stratix V PLL VCO frequency maxes out at 1.6 GHz. So 800 MHz is the max showing up in the datasheet for output clock of the PLL, (although the PLL mega wizard is letting me generate a 1 GHz clock using the integer PLL.  But getting it to do much of any logic at that speed will be very difficult to say the least.  Pete

[Altera_Forum]

As far as I know all FPGAs top out in the hundreds of MHZ range (except for serial transceivers). Some have Arm processors integrated. Some of these can operate with an internal clock at 1 GHZ.  

 The fastest (and most expensive) families are the Stratix from Altera and the Virtex from Xilinix.  The latest Quartus version is 15.0. There is a free version of modelsim available, but it runs slowly and can't handle large designs.

[Altera_Forum]

Looking at the upcoming Arria-10 switching characteristics. 

Maximum clock speed is 644MHz.

[Altera_Forum]

--- Quote Start ---  Although FPGA's have improved greatly since 2005, 1 GHz is still pushing the edge.  Is the data coming in on SERDIES?  Right now Stratix V PLL VCO frequency maxes out at 1.6 GHz. So 800 MHz is the max showing up in the datasheet for output clock of the PLL, (although the PLL mega wizard is letting me generate a 1 GHz clock using the integer PLL.  But getting it to do much of any logic at that speed will be very difficult to say the least.  Pete  --- Quote End ---   Thanks for the answer.  The 1GHz clock can be internal, it's not being fed externally. Also the output is much slower.  Basically, I have external circuit that trigger the FPGA, inside the FPGA, I need to synchronize the random trigger with the internal 1GHz clock. Then I am going to Demux it down to a slower clock speed.  If I can have 10 of the 8bits register that run at 1GHz, I can have a way to demux to a wider data at slower speed for processing.  Do you think Xilinx has faster FPGA that can run at 1GHz? Or it's just more of the same?  Thanks  Alan

[Altera_Forum]

--- Quote Start ---   The 1GHz clock can be internal, it's not being fed externally. Also the output is much slower.   --- Quote End ---   What is so special about running your internal logic at 1GHz?  Most practical systems that need to process digital data at a higher rate than the FPGA fabric can handle just process it in parallel, or as you refer to it, demux the data.  I have designs that interface to 1GHz ADCs and process data at 125MHz, and other designs that interface to 20GHz ADCs and process data at ~200MHz.  For practical FPGA designs (you try to fill up your expensive high-density FPGA), anything approaching 300MHz will start to get tricky to meet timing, and the FPGA will start to get hot :)  Cheers, Dave

[Altera_Forum]

As you notice by now, I am not a FPGA designer. Just an RF analog engineer contracted to company called Revera. I did design FPGA using Apex 10 years ago and was a success. I just learn what it takes to do the job and no more. I need to find the fastest FPGA to do the job, with minimal amount of "tricks" in design to get the job done. So I am willing to pay for a FPGA that is way over kill for this simple but fast task. It is not an issue to get a big one that I use only 10% as long as it has enough clock structure to support the task. 

 This is really a simple 16 channels event counter with coincident detector. But I need to detect if two channels receive trigger within 1nS and considers as being a single event that trigger both channels. If it is determined the trigger of the channels to be coincident, then I need to count as one event even though more than one channel receives a trigger.  So I need to sample 16 separate channels input at 1GHz as I need to determine coincidence between the channels. After that, it's just simple to sum the total events within 5uS and be read out.  It is very simple, but as you can see, I need to read all 16 channels at the same time with a 1nS clock. That will be at least one register being clocked at 1Ghz.  After that, I can quickly demux it out to say 8 different 16bit registers to perform coincident screening and add the total counts at 125MHz. BUT those 8 16 bit registers still have to meet the setup and hold time for 1GHz clocking even though it is being clocked at 125MHz.  Also, I need a 5 stage shift register right at the input of each of the 16 channels to generate signal to prevent retriggering and other things. those 5 X16 DFF has to be clocked synchronously at 1GHz before even performing demuxing and adding.   As you can see, the trigger of the 16 channels are coming in externally, the 1GHz clock is generated internal to the FPGA. The total count is being read out and reset the counter upon each reading. Just that simple!!!  Please advice what FPGA can do what I want. I suspect I need a FPGA that have enough registers and FF to do the job and the rest are quite empty!!!  Thanks

[Altera_Forum]

The serdes is the non fpga part of fpga!. It is not configurable logic but sometimes can be exploited. 

A Serdes channel accepts serial data at high frequencies(Gigas) and internally outputs parallel data to the fpga at slow fabric rate depending on chosen serialisation factor.  Thus you may be able to pass the fast channels and their tigger as serdes channels and see the slow parallel side if of any use in your specific task.

[Altera_Forum]

--- Quote Start ---  The serdes is the non fpga part of fpga!. It is not configurable logic but sometimes can be exploited. A Serdes channel accepts serial data at high frequencies(Gigas) and internally outputs parallel data to the fpga at slow fabric rate depending on chosen serialisation factor.  Thus you may be able to pass the fast channels and their tigger as serdes channels and see the slow parallel side if of any use in your specific task.  --- Quote End ---    thanks for the reply. can you give me a part number or a family of FPGA so I can read into it?

[Altera_Forum]

There are plenty of fpgas around that include serdes. I used startix iv years ago.

[Altera_Forum]

--- Quote Start ---  As you notice by now, I am not a FPGA designer. Just an RF analog engineer contracted to company called Revera.   --- Quote End ---   Thanks for describing your background, it makes it easier to help you.    --- Quote Start ---   This is really a simple 16 channels event counter with coincident detector. But I need to detect if two channels receive trigger within 1nS and considers as being a single event that trigger both channels. If it is determined the trigger of the channels to be coincident, then I need to count as one event even though more than one channel receives a trigger.  So I need to sample 16 separate channels input at 1GHz as I need to determine coincidence between the channels. After that, it's just simple to sum the total events within 5uS and be read out.   --- Quote End ---   What is the signal you are sampling at 1GHz? Is it an analog signal that needs a multi-bit ADC, or is it a signal that can be run through a high-speed comparator, and then that comparator output sampled?  You will face two issues with your external signal; you have to make it compatible with the digital FPGA pins, you have to synchronize it to the FPGA clock domain.    --- Quote Start ---   It is very simple   --- Quote End ---   No, its not simple. You have 16 different channels in 16 potentially different clock domains that you want to compare ...     --- Quote Start ---   I need to read all 16 channels at the same time with a 1nS clock. That will be at least one register being clocked at 1Ghz.   --- Quote End ---   But what about metastability? Does it matter if 16 FPGA registers sampling that same signal at 1GHz actually generate a change in logic state 1 clock apart due to metastability?    --- Quote Start ---   After that, I can quickly demux it out to say 8 different 16bit registers to perform coincident screening and add the total counts at 125MHz. BUT those 8 16 bit registers still have to meet the setup and hold time for 1GHz clocking even though it is being clocked at 125MHz.  Also, I need a 5 stage shift register right at the input of each of the 16 channels to generate signal to prevent retriggering and other things. those 5 X16 DFF has to be clocked synchronously at 1GHz before even performing demuxing and adding.    --- Quote End ---   The trigger filtering can be in the parallel domain, so I don't see this as an issue.    --- Quote Start ---   Please advice what FPGA can do what I want. I suspect I need a FPGA that have enough registers and FF to do the job and the rest are quite empty!!!   --- Quote End ---   The advice depends on what the external analog signal looks like.  For example, this board ...  https://www.ovro.caltech.edu/~dwh/carma_board/  contains an e2v 8-bit 1GHz ADC. This is what would be needed if your external signal was really "analog" and you had to look for a signal buried in noise, eg., a radar return pulse.  The FPGA on this board is the Stratix II. Altera has Stratix V devices now.  The features you can exploit on the FPGA are; the LVDS receivers operating at 1GHz, or the high-speed SERDES channel receivers operated in lock-to-refclk mode, so that the receivers are synchronously sampling. The SERDES might be a good option if you wanted to oversample the external signal, eg., operate at 4Gbps to sample the signal at 4GHz, and then use logic to detect the pulse and maybe decimate the sample stream. For both of these cases, your external signal needs to be converted to differential format with an amplitude of around 350mVpp to 400mVpp.  You could also use an external high-speed comparator and SERDES. In-Phi used to have a part with a 12Gbps comparator followed by a SERDES.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   What is the signal you are sampling at 1GHz? Is it an analog signal that needs a multi-bit ADC, or is it a signal that can be run through a high-speed comparator, and then that comparator output sampled? You will face two issues with your external signal; you have to make it compatible with the digital FPGA pins, you have to synchronize it to the FPGA clock domain.  --- Quote End ---    Wow, I don't know FPGA can receive analog signal now!!! The analog signal of each of the 16 channel is from a photomultiplier. The output pulse is analog with width of about 1nS and about 1mV amplitude. I am planning to have two opamp with gain of 10 each to amplify to about 100mV peak before driving a comparator to generate a digital pulse to drive the input of the FPGA. The pulses are TOTALLY asynchronous to the 1GHz internal clock. That's the reason I need shift registers in front to synchronize the random pulse to the internal clock.  You mean you have analog circuit inside the FPGA? Any chance to have amplifiers?     --- Quote Start ---  No, its not simple. You have 16 different channels in 16 potentially different clock domains that you want to compare ...    But what about metastability? Does it matter if 16 FPGA registers sampling that same signal at 1GHz actually generate a change in logic state 1 clock apart due to metastability?  --- Quote End ---   If metastability ONLY lasting 1 clock cycle, it will not be an issue. There are other uncertainties with counting pulses from photomultipliers. There is an at least 1:5 pulse height distribution of the output pulse, meaning one pulse can be as low as 0.2mV and the second can be as high as 1mV!!! So everything is a guessing. that's the reason we sum the total pulses in 5uS period and compare with the other 5us period.   If the metastable state last multiple clock period, then I will have a problem. metastable for one clock period will not cause problem.    --- Quote Start ---  contains an e2v 8-bit 1GHz ADC. This is what would be needed if your external signal was really "analog" and you had to look for a signal buried in noise, eg., a radar return pulse.  --- Quote End ---    You can have ADC in FPGA now?    --- Quote Start ---  The FPGA on this board is the Stratix II. Altera has Stratix V devices now.  The features you can exploit on the FPGA are; the LVDS receivers operating at 1GHz, or the high-speed SERDES channel receivers operated in lock-to-refclk mode, so that the receivers are synchronously sampling. The SERDES might be a good option if you wanted to oversample the external signal, eg., operate at 4Gbps to sample the signal at 4GHz, and then use logic to detect the pulse and maybe decimate the sample stream. For both of these cases, your external signal needs to be converted to differential format with an amplitude of around 350mVpp to 400mVpp.  You could also use an external high-speed comparator and SERDES. In-Phi used to have a part with a 12Gbps comparator followed by a SERDES.  Cheers, Dave  --- Quote End ---   Thanks Dave for the detail reply. This is totally new to me, I don't recall I can have analog input 10 years ago, basically FPGA were used in totally digital domain. does Stratix V have analog inputs?  I am not familiar with SERDES, what is In-Phi? Does SERDES have logic block that I can implement the coincident detector and adder?  Again, thanks for taking the time to educate me, it would take me a lot of reading to catch and I don't have time. I am trying to pick the closer ones, then spend the time to read the datasheet.  Alan

[Altera_Forum]

--- Quote Start ---   What is the signal you are sampling at 1GHz? Is it an analog signal that needs a multi-bit ADC, or is it a signal that can be run through a high-speed comparator, and then that comparator output sampled? You will face two issues with your external signal; you have to make it compatible with the digital FPGA pins, you have to synchronize it to the FPGA clock domain.  --- Quote End ---    Wow, I don't know FPGA can receive analog signal now!!! The analog signal of each of the 16 channel is from a photomultiplier. The output pulse is analog with width of about 1nS and about 1mV amplitude. I am planning to have two opamp with gain of 10 each to amplify to about 100mV peak before driving a comparator to generate a digital pulse to drive the input of the FPGA. The pulses are TOTALLY asynchronous to the 1GHz internal clock. That's the reason I need shift registers in front to synchronize the random pulse to the internal clock.  You mean you have analog circuit inside the FPGA? Any chance to have amplifiers?     --- Quote Start ---  No, its not simple. You have 16 different channels in 16 potentially different clock domains that you want to compare ...    But what about metastability? Does it matter if 16 FPGA registers sampling that same signal at 1GHz actually generate a change in logic state 1 clock apart due to metastability?  --- Quote End ---   If metastability ONLY lasting 1 clock cycle, it will not be an issue. There are other uncertainties with counting pulses from photomultipliers. There is an at least 1:5 pulse height distribution of the output pulse, meaning one pulse can be as low as 0.2mV and the second can be as high as 1mV!!! So everything is a guessing. that's the reason we sum the total pulses in 5uS period and compare with the other 5us period.   If the metastable state last multiple clock period, then I will have a problem. metastable for one clock period will not cause problem.    --- Quote Start ---  contains an e2v 8-bit 1GHz ADC. This is what would be needed if your external signal was really "analog" and you had to look for a signal buried in noise, eg., a radar return pulse.  --- Quote End ---    You can have ADC in FPGA now?    --- Quote Start ---  The FPGA on this board is the Stratix II. Altera has Stratix V devices now.  The features you can exploit on the FPGA are; the LVDS receivers operating at 1GHz, or the high-speed SERDES channel receivers operated in lock-to-refclk mode, so that the receivers are synchronously sampling. The SERDES might be a good option if you wanted to oversample the external signal, eg., operate at 4Gbps to sample the signal at 4GHz, and then use logic to detect the pulse and maybe decimate the sample stream. For both of these cases, your external signal needs to be converted to differential format with an amplitude of around 350mVpp to 400mVpp.  You could also use an external high-speed comparator and SERDES. In-Phi used to have a part with a 12Gbps comparator followed by a SERDES.  Cheers, Dave  --- Quote End ---   Thanks Dave for the detail reply. This is totally new to me, I don't recall I can have analog input 10 years ago, basically FPGA were used in totally digital domain. does Stratix V have analog inputs?  I am not familiar with SERDES, what is In-Phi? Does SERDES have logic block that I can implement the coincident detector and adder?  Again, thanks for taking the time to educate me, it would take me a lot of reading to catch and I don't have time. I am trying to pick the closer ones, then spend the time to read the datasheet.  Alan

[Altera_Forum]

Hi Alan:  

 Dave gave some good advice. Usually when dealing with data at that rate, it's coming into the FPGA through the Serdies or LVDS inputs:  Altera has serdies in their Cyclone, Arria, and Stratix Families, (Look for GX/GT in the part number)  Basically Cyclone is low end, Arria is mid range and Stratix is the high end parts. (Fasted, biggest, most power)  Pete

[Altera_Forum]

Hi 

 I posted a long thread this morning and it never show up. I even posted it again and nothing happen. It just said it will be waiting for moderator to moderate. Here is the original post:  quote=dwh@ovro.caltech.edu What is the signal you are sampling at 1GHz? Is it an analog signal that needs a multi-bit ADC, or is it a signal that can be run through a high-speed comparator, and then that comparator output sampled? You will face two issues with your external signal; you have to make it compatible with the digital FPGA pins, you have to synchronize it to the FPGA clock domain.   Wow, I don't know FPGA can receive analog signal now!!! The analog signal of each of the 16 channel is from a photomultiplier. The output pulse is analog with width of about 1nS and about 1mV amplitude. I am planning to have two opamp with gain of 10 each to amplify to about 100mV peak before driving a comparator to generate a digital pulse to drive the input of the FPGA. The pulses are TOTALLY asynchronous to the 1GHz internal clock. That's the reason I need shift registers in front to synchronize the random pulse to the internal clock.   You mean you have analog circuit inside the FPGA? Any chance to have amplifiers?     --- Quote Start ---  No, its not simple. You have 16 different channels in 16 potentially different clock domains that you want to compare ...     But what about metastability? Does it matter if 16 FPGA registers sampling that same signal at 1GHz actually generate a change in logic state 1 clock apart due to metastability?  --- Quote End ---   If metastability ONLY lasting 1 clock cycle, it will not be an issue. There are other uncertainties with counting pulses from photomultipliers. There is an at least 1:5 pulse height distribution of the output pulse, meaning one pulse can be as low as 0.2mV and the second can be as high as 1mV!!! So everything is a guessing. that's the reason we sum the total pulses in 5uS period and compare with the other 5us period.   If the metastable state last multiple clock period, then I will have a problem. metastable for one clock period will not cause problem.   quote=dwh@ovro.caltech.edu  contains an e2v 8-bit 1GHz ADC. This is what would be needed if your external signal was really "analog" and you had to look for a signal buried in noise, eg., a radar return pulse.   You can have ADC in FPGA now?   quote=dwh@ovro.caltech.edu  The FPGA on this board is the Stratix II. Altera has Stratix V devices now.   The features you can exploit on the FPGA are; the LVDS receivers operating at 1GHz, or the high-speed SERDES channel receivers operated in lock-to-refclk mode, so that the receivers are synchronously sampling. The SERDES might be a good option if you wanted to oversample the external signal, eg., operate at 4Gbps to sample the signal at 4GHz, and then use logic to detect the pulse and maybe decimate the sample stream. For both of these cases, your external signal needs to be converted to differential format with an amplitude of around 350mVpp to 400mVpp.   You could also use an external high-speed comparator and SERDES. In-Phi used to have a part with a 12Gbps comparator followed by a SERDES.    Thanks Dave for the detail reply. This is totally new to me, I don't recall I can have analog input 10 years ago, basically FPGA were used in totally digital domain. does Stratix V have analog inputs?   I am not familiar with SERDES, what is In-Phi? Does SERDES have logic block that I can implement the coincident detector and adder?   Again, thanks for taking the time to educate me, it would take me a lot of reading to catch and I don't have time. I am trying to pick the closer ones, then spend the time to read the datasheet.   Alan

[Altera_Forum]

--- Quote Start ---   I posted a long thread this morning and it never show up. I even posted it again and nothing happen. It just said it will be waiting for moderator to moderate.  --- Quote End ---    You can send it to me directly (my forum name is my email address) and I'll post it.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  You can send it to me directly (my forum name is my email address) and I'll post it.  Cheers, Dave  --- Quote End ---    Do you mean email to dwh@ovro.caltech.edu?

[Altera_Forum]

I copied and sent the original post to you at email address: dwh@ovro.caltech.edu

[Altera_Forum]

Post received from Alan via email: 

   --- Quote Start ---   What is the signal you are sampling at 1GHz? Is it an analog signal that needs a multi-bit ADC, or is it a signal that can be run through a high-speed comparator, and then that comparator output sampled? You will face two issues with your external signal; you have to make it compatible with the digital FPGA pins, you have to synchronize it to the FPGA clock domain.  --- Quote End ---    Wow, I don't know FPGA can receive analog signal now!!! In my project,the analog signal of each of the 16 channel is from a photomultiplier. The output pulse is analog with width of about 1nS and about 1mV amplitude. I am planning to have two opamp with gain of 10 each to amplify to about 100mV peak before driving a comparator to generate a digital pulse to drive the input of the FPGA. The pulses are TOTALLY asynchronous to the 1GHz internal clock. That's the reason I need shift registers in front to synchronize the random pulse to the internal clock.  You mean you have analog circuit inside the FPGA? Any chance to have amplifiers?     --- Quote Start ---  No, its not simple. You have 16 different channels in 16 potentially different clock domains that you want to compare ...  But what about metastability? Does it matter if 16 FPGA registers sampling that same signal at 1GHz actually generate a change in logic state 1 clock apart due to metastability?  --- Quote End ---    If metastability ONLY lasting 1 clock cycle, it will not be an issue. There are other uncertainties with counting pulses from photomultipliers. There is an at least 1:5 pulse height distribution of the output pulse, meaning one pulse can be as low as 0.2mV and the second can be as high as 1mV!!! So everything is a guessing. that's the reason we sum the total pulses in 5uS period and compare with the other 5us period.   If the metastable state last multiple clock period, then I will have a problem. metastable for one clock period will not cause problem.    --- Quote Start ---  contains an e2v 8-bit 1GHz ADC. This is what would be needed if your external signal was really "analog" and you had to look for a signal buried in noise, eg., a radar return pulse.  --- Quote End ---    You can have ADC in FPGA now?    --- Quote Start ---  The FPGA on this board is the Stratix II. Altera has Stratix V devices now.  The features you can exploit on the FPGA are; the LVDS receivers operating at 1GHz, or the high-speed SERDES channel receivers operated in lock-to-refclk mode, so that the receivers are synchronously sampling. The SERDES might be a good option if you wanted to oversample the external signal, eg., operate at 4Gbps to sample the signal at 4GHz, and then use logic to detect the pulse and maybe decimate the sample stream. For both of these cases, your external signal needs to be converted to differential format with an amplitude of around 350mVpp to 400mVpp.  You could also use an external high-speed comparator and SERDES. In-Phi used to have a part with a 12Gbps comparator followed by a SERDES.  Cheers, Dave  --- Quote End ---     Thanks Dave for the detail reply. This is totally new to me, I don't recall I can have analog input 10 years ago, basically FPGA were used in totally digital domain. does Stratix V have analog inputs?  I am not familiar with SERDES, what is In-Phi? Does SERDES have logic block that I can implement the coincident detector and adder?  Again, thanks for taking the time to educate me, it would take me a lot of reading to catch and I don't have time. I am trying to pick the closer ones, then spend the time to read the datasheet.  Alan

[Altera_Forum]

Hi Alan, 

 You have misunderstood. I was warning you that an FPGA expects a digital signal. Re-read my post. The digital signal requirements for LVDS and SERDES are that the signal amplitude be 350mVpp to 400mVpp. If your signals do not have many toggles, then they would also need to be DC coupled to the digital inputs, with an appropriate bias voltage applied.  Your signal *does not* meet these requirements, so you need to decide how you are going to interface your signal to the FPGA.  The board I provided a link to has a dual 1GHz ADC interfaced to an FPGA. The ADC is *not* part of the FPGA.  If you only care about the time at which your pulses occur, and not their amplitude, then you might be able to use a limiting amplifier with high gain, and then interface that to the FPGA inputs.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---   I am not familiar with SERDES   --- Quote End ---   SERDES = serializer/deserializer. Its a fancy name for a high-speed parallel-to-serial shift-register in the transmit path, and a high-speed serial-to-parallel shift-register in the receive path. FPGAs have hardened silicon blocks in their I/O cells that can operate at up to 28Gbsps in the highest (most expensive) devices. The lower-end devices have 3.5Gbps SERDES.    --- Quote Start ---   what is In-Phi?   --- Quote End ---   Its a company. Google it.    --- Quote Start ---   Does SERDES have logic block that I can implement the coincident detector and adder?   --- Quote End ---   No, not for your application. The SERDES blocks have pattern detectors that can be used for digital link byte/word-alignment.    --- Quote Start ---   Again, thanks for taking the time to educate me, it would take me a lot of reading to catch and I don't have time. I am trying to pick the closer ones, then spend the time to read the datasheet.   --- Quote End ---   Take the time to read, and re-read the advice people give you, then ask more questions.  Cheers, Dave