Looking for help on constraint syntax

[GD76]

There is a setup slack violation (see attached). The timing violation at RAM_CONTROL:i13|q3 to DSACK1. We are off by 2.477ns. Looking to understand what syntax for CPLD can be constructed to constraint the path. 

Adding the SLOW_SLEW_RATE to the IO in DSACK1 in assignment editor and setting it as OFF works. But looking for a solution more embedded in making the tool route internal path. Any help apprecieted.

[sstrell · Accepted solution]

If I'm reading your document correctly, you're transferring between a 40 MHz clock domain and a 20 MHz clock domain.  As such, you need a multicycle timing exception in your .sdc file.  Going from a faster to a slower domain usually requires a -start multicycle to select the correct launch edge for the setup and hold analysis:

set_multicycle_path –from SYSCLK –to CLK20MHZSYS_ext –setup –start 2 

set_multicycle_path –from SYSCLK –to CLK20MHZSYS_ext –hold –start 1 

[GD76]

The CPLD gets 20MHz clock. The SYSCLK is 20MHz. Not sure where you got the 40MHz from.

[sstrell]

Your launch edge time is at 25, so I thought it was 40 MHz.  Can you show a screenshot of the waveform view in your timing analysis?

[GD76]

Here is the waveform. So the clock need to delayed by 50ns.

[sstrell]

So you're launching on the falling edge and you want to latch not on the next rising edge but the rising edge after what's in your screenshot?  So a period and a half?  Maybe:

set_multicycle_path –fall_from SYSCLK –to CLK20MHZSYS_ext –setup –end 2 

set_multicycle_path –fall_from SYSCLK –to CLK20MHZSYS_ext –hold –end 1 

[sstrell]

set_multicycle_path –fall_from SYSCLK –to CLK20MHZSYS_ext –setup –end 2 

set_multicycle_path –fall_from SYSCLK –to CLK20MHZSYS_ext –hold –end 1 

[GD76]

DSACK1 is launching at falling edge, but want delay it to next falling edge. In this case half-period is 25ns, so 50ns.

So, I have  external clock as 50ns, half-period 25ns

create_clock -name {SYSCLK} -period 50.000 -waveform { 0.000 25.00 } [get_ports {SYSCLK}]

From the above, creating a virtual clock

create_clock -name {CLK20MHZSYS_ext} -period 50.000

The signal of interest constraint as below and give setup slack timing violation. How to make this delayed?

set_output_delay -clock CLK20MHZSYS_ext -max 7.5 [get_ports {DSACK1_n}]
set_output_delay -clock CLK20MHZSYS_ext -min 0.5 [get_ports {DSACK1_n}]

Then tried add this but still give violation

set_output_delay -clock CLK20MHZSYS_ext -clock_fall 50.000 [get_ports {DSACK1_n}]

[sstrell]

-clock_fall is a switch indicating, for output delay, that data is captured on the falling edge of the virtual clock.  I'm not sure why you have "50.000" there.  You would still need -max and -min with 7.5 and 0.5, respectively.

So I'm still not clear what you want.  Are you saying you want this signal launched by a falling edge (SYSCLK) and latched by the next falling edge of CLK20MHZSYS_ext?  If you clarify exactly what edges you want to use for launch and latch, maybe even a diagram, that would help.