MAX 10 LVDS and DDR

[Altera_Forum]

I haven't used LVDS before, and I want to interface to an 12-bit 125-MSPS ADC running 6-bit LVDS with DDR. Does the MAX 10 LVDS interface support this? If not, can I still use the MAX 10 LVDS interface, but with some additional HDL for DDR?

[Altera_Forum]

Yes, MAX 10 can do this for you. Read through chapter 4, "MAX 10 LVDS Receiver Design" of the "max 10 high-speed lvds i/o user guide (https://www.altera.com/literature/hb/max-10/ug_m10_lvds.pdf)". Use the "Altera Soft LVDS" IP core, configured for RX to implement the interface. Depending on the clock/data relationship from your ADC you'll need to adjust the deserialization factor. Yes, you may need additional logic. However, this will be to piece together complete ADC values from consecutive 'rx_out' values. Depending on how your ADC is/can be configured you may no need this. 

 Cheers, Alex

[Altera_Forum]

That's what I was hoping for. Thanks! :)

[Altera_Forum]

You are not in the clear yet: the maximum rate is around 720 Mbit/s which is less than 1.5 Gbits you quoted in your original post. Have you decided on which ADC?

[Altera_Forum]

It's a 6-bit wide interface with DDR so it should run at the sample rate of 125 MSPS. 

 I have chosen the ADC, but I don't have the part# right now

[Altera_Forum]

250 Mbit/s will of course go fine.

[Altera_Forum]

I'm trying to do more or less the same thing, interfacing the MAX 10 with an LTC2264 40 Mhz ADC.  

 http://cds.linear.com/docs/en/datasheet/22654312fb.pdf - page 9  The output from the ADC is LVDS serial, at double data rate, an LVDS clock signal, and an LVDS frame signal. I have several questions.  After reading the MAX 10 High-Speed LVDS manual, I'm confused as to the clocking scheme I should use for a soft LVDS receiver block. Since the ADC provides me with a serial clock, I shouldn't need to use a PLL in the LVDS block, should I? What PLL configuration should I use when configuring this IP?  Second question: word boundary alignment. The ADC has a frame output, with a differential 0 to 1 logic transition indicating the first bit of the serial word. I noticed in the MAX 10 LVDS doc that there is a data re-alignment block in the LVDS signal chain - I'm guessing that the rx_channel_data_align input should be from the ADC frame signal?  Third question: the soft LVDS module instantiation port list shows an RX serial data input with one bit per LVDS channel. Why does an LVDS block appear to take single ended inputs? I must be missing something there.  Fourth question, double rate rate. In the MAX 10 LVDS doc, there is only one mention of DDR: "For LVDS transmitters and receivers, MAX 10 devices use the the double data rate I/O (DDIO)registers that reside in the I/O elements (IOE)." Does this mean that the LVDS serial input is assumed to be using double data rate, and that I do not need to either specify DDR anywhere?  Finally, why can't I use primitives like ALTDDIO or ALT_INBUF_DIFF with the MAX 10? I have a design for this same ADC using equivalent primitives for Xilinx FPGAs, and it not only makes the HDL stupidly easy to comprehend, but would only take me about a half hour to bang out the same design for Altera if I could use them.  I would appreciate any help here.  Thanks, Devin

[Altera_Forum]

You don't need a PLL as the output clock DCO is centre-aligned to the output data, OUTA and OUTB, and the frame signal FR. 

For word alignment: feed the FR signal into a DDR-In like the data and use the 01 transition (or the 10 transition) as the word-alignment indicator. The other questions become clear when you study the Altera GPIO-Lite core in the max 10 general purpose i/o user guide