The MAX 10 A/D block diagram shows a sample and hold function before the A/D. Unfortunately, there is no documentation of the timing for the S/H function. When sampling a complex signal, it is important to know what the sample window is and what the relationship is between the A/D command and whether the S/H is in the "sample" or "hold" condition and how long it takes to stabilize so the A/D can have a stable value. The A/D user's guide is silent on this function. My local Arrow rep has been unable to get any feedback from Intel on these details.
Does anyone have any information on how the S/H stage works, what its timing is and how it is related to the conversion command/clock for the A/D?
The input clock frequencies are 2 MHz, 10 MHz, 20 MHz, 40 MHz, and 80 MHz.
Implementation Guide reference: https://www.intel.com/content/www/us/en/programmable/documentation/sam1393576011848.html
I have read all of that documentation before. The block diagram early in that file that shows the "ADC Hard IP Block" shows a sample/hold amplifier before the A/D converter, but nowhere have I been able to find any documentation of how the S/H function is controlled and when it switches from "sample" mode to "hold" mode for the A/D converter. I need to convert a signal with limited valid level timing (500kHz sample rate) so I need to understand the timing of the S/H function so I can control the phasing between the S/H and the analog input. The S/H must switch from "sample" to "hold" during the valid level time on the analog input so the A/D has a stable input signal to convert. It's not a matter of what clock frequency I'm using. I need to know more about the timing of the S/H function with respect to the A/D control signals.
This function is in the IP, user has to concern only the parameters of the entire IP. According to the user guide, 500kHz is one of the allowed values for sampling rate. As long as the value is an allowed value for the sampling rate, you will be able to see the expected result.