Is using an external clock without a clock buffer causing any problem?
I'm implementing SPI slave. An external SPI clock is directly from a pin(not a clock pin, but just an IOpin) of the FPGA(10M08SAE144C8G). Should I use a clock buffer for this? The reason why I have this question is I got some timing violations. Here are my simple codes. ----------------------------------------------------------------- always @(negedge sclk or posedge in_CSn) if (in_CSn) Cnt <= 3'd7; else if (Cnt == 3'd0) Cnt <= 3'd0; else Cnt <= Cnt - 1'b1; assign out_MISO = (~in_CSn)? pData[Cnt] : 1'b0; ----------------------------------------------------------------- And the timing violations are from "Cnt". These are very simple logics, But I cannot understand why this causes timing violations. Timing report shows this clock's restricted fMax is 250Mhz.链接已复制
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What speed are you trying to run your SPI at? An ordinary I/O pin should quite happily be able to operate as a clock for a small amount of logic.
Have you posted all the code driven by sclk? How have you constrained your design? If so then I suspect your constraints are not quite right. Add them to the post. Cheers, AlexThanks Alex for our reply!
- How have you constrained your design? Not yet, cause I thought actual this SPI clock (sclk) is not that fast as less than 50 Mhz. Please give me some hints. I recently moved from Xilinx to Altera. I'm going to look at tutorial adding constraint file, but I'll be happy if you give me some tips making less mistakes. Regards,Be careful, your design is not fully synchronous so it complicates the timing constraints.
You should not have in_CSn in your sensitivity list to be fully synchronous with the sclk signal, and in your case, you probably want to be synchronous with sclk. --- Quote Start --- always @(negedge sclk or posedge in_CSn) if (in_CSn) Cnt <= 3'd7; else if (Cnt == 3'd0) Cnt <= 3'd0; else Cnt <= Cnt - 1'b1; --- Quote End ---You have no timing constraints? What 'timing violations' are being reported?
What hardware are you using? Is the FPGA your a host talking to an external slave device? You mention a 50MHz clock. What hardware are you using? Assuming you are trying to talk to an external slave and you'd simply like to get something working I suggest you use the 50MHz clock to clock all your logic and treat your sclk as a signal (not a clock) that you generate with logic. You are going to need more of a state machine to implement an SPI host as well. JRL - whilst I agree this may not be ideally coded, the code does conform to the classic clock & (asynchronous) reset in the sensitivity list with a single conditional statement (if) handling the reset (in_CSn). So, I feel Quartus will have no trouble understanding this or timing it. Cheers, Alex