MAX V - UFM IP core signals remain undefined when I try to simulate using a test bench

[VR_S]

I have implemented a system where I store a 3 bit value to the UFM in my CPLD using a 'SET' signal, and read that value from the UFM using a 'GET' signal.

The system is running on the board partly (Enough to know the UFM is storing data and responding to read signal - using LEDs), but when I simulate using a testbench on modelsim - all the signals going into UFM and coming out is undefined. All the other signals are working fine.

Using MAX V CPLD
- Quartus Prime 

- Modelsim

Do I need to include any UFM IP core library to my TB file? If so, please let me know how to do that?

Warnings:
- ** Warning: (vsim-3473) Component instance "ufm_parallel_0 : UFM_Config_ufm_parallel_0" is not bound.

- ** Warning: (vsim-8684) No drivers exist on out port /ufm_tb/UUT/ufm_inst/data_valid, and its initial value is not used.

- ** Warning: (vsim-8684) No drivers exist on out port /ufm_tb/UUT/ufm_inst/dataout, and its initial value is not used

- ** Warning: (vsim-8684) No drivers exist on out port /ufm_tb/UUT/ufm_inst/nbusy, and its initial value is not used.

It would be a great help.

Thanks 

VR_S

[VR_S]

To fix the bound issue:
How do I add the source file of component to the simulation test bench?

[IntelSupport]

Hi Raj,

There is few debug steps from the link below related to your issue. Can you verify all those suggestion and let me know.

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Warning-vsim-3473-Component-instance-quot-mem-map-system-mem/td-p/1385105

[IntelSupport]

May I know if there is any update?

[IntelSupport]

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