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Write-protect configuration flash memory with Quartus Prime Pro Programmer

Paul_S
Beginner
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In our design we use a Micron MT25QU256 flash memory device to hold the configuration for the Cyclone 10 GX FPGA.   We are going to load a factory image and an application image into this memory, and we want to write-protect the factory image.

 

I understand that there is a way to write-protect sections of the flash device using IP blocks that are built into the firmware design.   Is there also a way to apply write protection using the Quartus Prime Pro Programmer tools?   This would allow us to apply the protection immediately when we first program the device.

 

Thanks in advance!

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lixy
Employee
1,061 Views

Hi,


I wonder if the item you are working on is something like Development Kit.

Are you using the AS scheme now?


Thanks & Regards,

Xiaoyan


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Paul_S
Beginner
1,014 Views

Hi Xiaoyan,

Yes, our configuration scheme is similar to the one on the Intel Cyclone 10 GX Development Kit.   We have implemented both the AS x4 and JTAG configuration schemes in our design.

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lixy
Employee
1,001 Views

Hi Paul,


The Programmer can not implement the image protection by itself.

Generally, the protection of Factory Image is implemented by setting a fixed address to user application.

As you said, there's a Serial Flash Interface IP that can implement this write-erase protecting feature to certain vector range. Is it what you are referring to?

Also, are you using .jic or .pof for configuration?


Thanks & Regards,

Xiaoyan


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Paul_S
Beginner
997 Views

Hi Xiaoyan,

I was planning to use the ASMI Parallel IP core, which implements protection for various ranges of sectors, starting with a single sector up to the entire device.   Does the Serial Flash Loader support implementing write protection?   As far as I could see, it is a logic bridge between the JTAG and AS interfaces.   Perhaps there is a specific set of JTAG commands that would allow write-protection to be set on the flash memory through the SFL?   We're using a .jic for configuration of the flash over JTAG.

Thanks for your time on this.

Paul

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lixy
Employee
983 Views

Hi Paul,


As for your question about Serial Flash Interface IP, you may check the "Generic Serial Flash Interface Intel FPGA IP User Guide". In the Chapter 1.8, there's an example of how to protect certain sector range of FLASH, which is based on a platform built with this IP.

You may check this chapter first and see if it is helpful.


Thanks & Regards,

Xiaoyan


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Paul_S
Beginner
980 Views

Hi Xiaoyan,

I had a quick look, it seems like it might work.   I could connect the serial flash memory to the JTAG interface using the JTAG to Avalon bridge and the Generic Serial Flash Interface IP.   Then I could run a TCL script in the Quartus System Console that is able to access the registers on the Avalon bus, including the control and status register that sets the protection.

Does that sound right to you?

Paul 

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lixy
Employee
955 Views

Hi Paul,

Yeah, You are correct.


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lixy
Employee
951 Views

Hi Paul,

By the way, the "ASMI parallel IP" is actually old now. Now we recommend users to use the Generic Serial Flash Interface IP.


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lixy
Employee
910 Views

Hi Paul,

Any further questions?

Thanks,

Xiaoyan


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Paul_S
Beginner
882 Views

Thanks Xiaoyan,

I tried creating a design with the Generic Serial Flash and an JTAG to Avalon Bridge, and was able to communicate with the flash memory registers using System Console, so this may be a potential solution.   Unfortunately this method doesn't seem to work using the default Serial Flash Loader image that Quartus Programmer uses to program .jic files into flash; if it did, that would be perfect.

Up until now we have used the ASMI Parallel IP core for remote firmware update in our design, because it allowed us to implement it without using an Avalon memory-mapped slave interface.   The Generic Serial Flash IP forces us to use the Avalon interface, which would require a major change to the register architecture that we currently use.   Do you have an idea of how much longer Intel will continue to support the ASMI Parallel IP core?

Also, does the Generic Serial Flash IP core support multiple masters on the Avalon bus?   If we did use this IP core we would like to be able to control it both from JTAG and another source to support remote firmware update.

Thanks,

Paul

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WZ2
Employee
764 Views

Hi,

 

ASMI Parallel IP currently does not have the discontinuance notification, which means Intel has not started planning its EOL. 

About the second question about "Multi-master" for Generic Serial FLASH loader IP, you can implement the multi-master in your design. It is not implemented by the IP itself. 


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WZ2
Employee
741 Views

Hi there

Any further question~


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Paul_S
Beginner
671 Views

Thanks WZ2, I think that has answered all my questions on this topic.

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