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TBarn2
Beginner
1,045 Views

MAX10 10M04CE using FIR IP

Hi we have a new board design that uses a 10M04CE device. We are experimenting with functionality. We would like to implement an FIR filter and have tried to create one using the FIR II IP in the Quartus development system. Unfortunately this ends up giving an error like: "Error (16031): Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM. File: /src/BMeasure1/fpga/test013-dsp/quartus/db/altsyncram_8ot3.tdf Line: 34 "

I understand that the MAX10 CE "compact" FPGA's cannot do memory initialisation from FLASH. That is ok, as I can use the FIR's ability to write to the coefficient memory. But I cannot see how to create an FIR IP block that has a fixed number of coefficient taps but with no initial cooeficient values that would allow this to work.

Is this possible or will I have to roll my own FIR ?

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7 Replies
Nooraini_Y_Intel
Employee
134 Views

Hi,

 

Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you.

 

Regards,

Nooraini

 

TBarn2
Beginner
134 Views

No we haven't had an answer to this. We are expecting to have to roll our own rather than use the provided IP.

CheePin_C_Intel
Employee
134 Views

Hi Tbarn2,

 

As I understand it from the initial description, it seems like you have some inquiries related to the FIR II IP coefficient as following:

"But I cannot see how to create an FIR IP block that has a fixed number of coefficient taps but with no initial coefficient values that would allow this to work.

Is this possible or will I have to roll my own FIR ?

"

 

Just wonder if you are referring to creating a FIR II instance without default coefficient value? If yes, for your information, by default, the FIR II IP will have a default value of coefficient and user can configure the coefficient based on his/her own need. You may probably workaround by importing your coefficient to the IP during the FIR II IP instantiation.

 

Please let me know if my understanding of your inquiry is incorrect.

 

Thank you.

 

Chee Pin

TBarn2
Beginner
134 Views

Yes, but the MAX10 CE "compact" FPGA's cannot do memory initialisation from FLASH. Which means if you try and create an FIR IP instance with any default coefficients defined the project won't build. So ideally what is needed is the ability to just set the number of coefficients, with no default initialisation, and allow these coefficients to be set during runtime. Or is there a workaround for this?

 

Without something like this the current FIR IP cannot be used on a MAX10 CE "compact" FPGA.

 

Terry

CheePin_C_Intel
Employee
134 Views

Hi,

 

Would you mind to let me know the specific part that you are using? For your information, I have tested with a simple design with one FIR II instance with default settings in 10M50SCE144I7G in Q18.1Std, the design can pass Fitter compilation without issue.

Please let me know if there is any concern. Thank you.

 

Chee Pin

TBarn2
Beginner
134 Views

I have tried building for a 10M04SCE144C8G and an 10M02SCE144C8G. Building using 18.0.0 Build 614 04/24/2018 Lite Edition. A multi-channel FIR II design with programmable coefficients for these two fail with error messages:

 

...

Error (16031): Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM.

Error (16031): Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM.

Error (16031): Current Internal Configuration mode does not support memory initialization or ROM. Select Internal Configuration mode with ERAM.

Error: Quartus Prime Analysis & Synthesis was unsuccessful. 48 errors, 17 warnings

   Error: Peak virtual memory: 1209 megabytes

   Error: Processing ended: Thu Nov 8 09:07:29 2018

   Error: Elapsed time: 00:00:18

   Error: Total CPU time (on all processors): 00:00:44

Error (293001): Quartus Prime Full Compilation was unsuccessful. 50 errors, 17 warnings

 

CheePin_C_Intel
Employee
134 Views

Hi,

 

For your information, I am able to compile a FIR II IP in both the 10M04SCE144C8G and an 10M02SCE144C8G part that you are using. As I discussed with the configuration expert, I understand that the compact Max 10 that you are using does not support memory ie ROM initialization. If you have any ROM in your design, it will trigger the errors that you are seeing. Just wonder if you are using any module which require memory initialization ie ROM in your design?

 

 

Thank you.

 

Chee Pin

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