Hi All,I am debugging PCBs containing a design using the MAX10x50SCE144. All the banks except 5 & 6 run at 3.3V and banks 5 & 6 run at 2.5V for receiving SUB-LVDS signals. Accordingly I have added the recommended external bias networks to those signals (seen on the right-side of the schematic, some are chopped off). My problem is this: on two out of two boards that I've applied power to, the 2.5V supply is being pulled up to 3.3V. On the first board, I measured a bi-directional short between the supplies of 2.7 ohms. After looking carefully under a microscope for hours, I removed and replaced the FPGA. The short is gone, but the supply is still pulled to 3.3. I have entered a design into the Quartus Lite tools, including my intended bank voltages, and it has not complained that I'm doing anything to violate the part parameters. I just thought I'd bounce the design off you as a double-check. All comments welcome. Thanks, Scott
There is no scope inside the FPGA for it to 'short' these supplies together. Or indeed pull banks 5 & 6 to 3.3V via the other bank supplies.You either have a design fault or a build fault. The fact you've changed the FPGA and changed the symptom suggests you had a build fault - I'd be guessing as to what that was without more detail. However, given the 2.5V rail is still showing 3.3V I suggest you still have a design fault or a further build fault. Did you, by chance, power the board when the FPGA was removed? Is your 2.5V supply giving out 2.5V - or 3.3V? The schematic you've posted isn't readable (a common problem with images posted here). Perhaps try and post it again. Cheers, Alex
I had a similar problem that resulted from connecting Bank 1A to 3.3V and Bank 1B to 2.5V. They are connected internally so 2.5V got pulled up to 3.3V. Sounds like your situation is different, but maybe this gives a clue.