On CFM0 - I have a boot image. With the boot I program a main image on CFM1.
First I switch to CFM0 with a micro controller pins
BOOT_SEL = 0 ENA = 0 Delay(100) ENA = 1
Then I download the main image - main_0.rpd (with a big endian checkbox checked) .
After a successful image download I switch to CFM1
BOOT_SEL = 1 ENA = 0 Delay(100) ENA = 1
And I see no response from FPGA.
What could be a problem? What do I miss?
The main image - should it include dual config module?
component dual_config is port ( avmm_rcv_address : in std_logic_vector(2 downto 0) := (others => '0'); -- avalon.address avmm_rcv_read : in std_logic := '0'; -- .read avmm_rcv_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata avmm_rcv_write : in std_logic := '0'; -- .write avmm_rcv_readdata : out std_logic_vector(31 downto 0); -- .readdata clk : in std_logic := '0'; -- clk.clk nreset : in std_logic := '0' -- nreset.reset_n ); end component;
I mean it switched to CFM1 page but no reaction from the main program. It seems like CFM1 loaded OK - STATUS and CONF_DONE pins behave as expected.
To analyze the problem further I did the following - created a combined pof file
first page - boot.sof (CFM01)
second page - main.sof (CFM1)
Then I burn the pof file, switch to CFM1 - and no reaction from the main program.
When I burn the main.pof only - everything OK.
Oh...seems like my stupid mistake. Now it's OK.