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Altera_Forum
Honored Contributor I
3,505 Views

MAX10 FPGA versus Cyclone V

Hi, 

I wrote some VHDL code for the Cyclone V FPGA with ALTLVDS_RX function. 

Can I use the same code for the MAX10 FPGA? 

 

Regards.
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14 Replies
Altera_Forum
Honored Contributor I
850 Views

Why don't you try it?

Altera_Forum
Honored Contributor I
850 Views

If not mistaken, the Max10 support LVDS using soft logic serdes. I think the same CV ALTLVDS_RX might not work if you compile directly. But you could give it a try also. If not working, then try re-instantiate the IPs.

Altera_Forum
Honored Contributor I
850 Views

 

--- Quote Start ---  

Why don't you try it? 

--- Quote End ---  

 

 

yeah.... just change the device selection and spend a little bit of time to see what is the compilation result.
Altera_Forum
Honored Contributor I
850 Views

You can also check in the ALTLVDS_RX user guide to see if there is any device family support list.

Altera_Forum
Honored Contributor I
850 Views

what usage you downgrade from cyclone V to MAX10??

Altera_Forum
Honored Contributor I
850 Views

Probably to save the cost of flash since Max devices support on chip memory for configuration.

Altera_Forum
Honored Contributor I
850 Views

I think the best would to be try out compilation with design in both device to see if can fit or not. Max 10 is of much lesser logic as compare to CV.

Altera_Forum
Honored Contributor I
850 Views

MAX10 is a huge downgrade in term of performance compared to cyclone V. your usage really that simple allow you for such down grade?

Altera_Forum
Honored Contributor I
850 Views

Agree with pororo. Generally switch from FPGA to CPLD might bump into logic resource concern.

Altera_Forum
Honored Contributor I
850 Views

Don't get confused by MAX 10 classification as "CPLD". It's a full featured FPGA with flash configuration memory and can well keep up with previous FPGA families like Cyclone III and has quite similar logic core features.

Altera_Forum
Honored Contributor I
850 Views

The other MAX devices are more like FPGAs than CPLDs.

Altera_Forum
Honored Contributor I
850 Views

By looking at the overview chapter of Max 10 and CV handbook, the smallest devices' LE is 2k (Max10) vs 25k (CIV) which seems to be significant.

Altera_Forum
Honored Contributor I
850 Views

i believe cost is not your constraint as you started in cyclone V at the first place, so just stick to cyclone V, better support in feature.

Altera_Forum
Honored Contributor I
850 Views

I think it would be back to the initial requirement of your design and applications. Need to evaluate if you can achieve the design in Max or need Cyclone. You can sit with your local FAE for part selection. Or you can also use the part selector tool in Altera web to assist in part selection.

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