Hi,I wrote some VHDL code for the Cyclone V FPGA with ALTLVDS_RX function. Can I use the same code for the MAX10 FPGA? Regards.
If not mistaken, the Max10 support LVDS using soft logic serdes. I think the same CV ALTLVDS_RX might not work if you compile directly. But you could give it a try also. If not working, then try re-instantiate the IPs.
--- Quote Start --- Why don't you try it? --- Quote End --- yeah.... just change the device selection and spend a little bit of time to see what is the compilation result.
Don't get confused by MAX 10 classification as "CPLD". It's a full featured FPGA with flash configuration memory and can well keep up with previous FPGA families like Cyclone III and has quite similar logic core features.
I think it would be back to the initial requirement of your design and applications. Need to evaluate if you can achieve the design in Max or need Cyclone. You can sit with your local FAE for part selection. Or you can also use the part selector tool in Altera web to assist in part selection.