If not mistaken, the Max10 support LVDS using soft logic serdes. I think the same CV ALTLVDS_RX might not work if you compile directly. But you could give it a try also. If not working, then try re-instantiate the IPs.
--- Quote Start --- Why don't you try it? --- Quote End --- yeah.... just change the device selection and spend a little bit of time to see what is the compilation result.
Don't get confused by MAX 10 classification as "CPLD". It's a full featured FPGA with flash configuration memory and can well keep up with previous FPGA families like Cyclone III and has quite similar logic core features.
Professionally speaking, assuming that because I was able to buy a few Cyclone development boards (more capable than I need for most of my designs) automatically means I can afford to purchase 10,000 more Cyclone V chips just for production, would be extremely unprofessional. I'm sure you know it is very unlikely that any of my projects use exactly every feature of my development board.
I'm not saying you don't know this but: Always look at the design, once completed, and choose the less-capable chip that can handle that design with a more reasonable price. It sounds very much like this is what they were asking for.
I think it would be back to the initial requirement of your design and applications. Need to evaluate if you can achieve the design in Max or need Cyclone. You can sit with your local FAE for part selection. Or you can also use the part selector tool in Altera web to assist in part selection.