MAX10 JTAG Secure Design Example unlock

[DamBam]

Hi,

I'm struggling with a unlock instruction in mentioned example. The problem is that when I trigger unlock instruction the Quartus Programmer can't accces JTAG chain (Can't Porgram pof/sof, erase, verify). Porgrammer prints the following message:

Error (209040): Can't access JTAG chain
Error (209040): Can't access JTAG chain
Error (209012): Operation failed

Interesting thing is that described issue doesn't occur when I power-cycle the devboard and trigger unlock instruction then.

So the question is,  should the unlock instruction give the control of the JTAG Control Block back to external interface?

and if the answer is positive why it's only done once after power-up?

Thanks in advance

DB

[NurAiman_M_Intel]

Hi DB,

Thank you for contacting Intel community.

For Max 10 design example unlock, have you refer to the design example page and follow the instruction in the document?https://fpgacloud.intel.com/devstore/platform/15.0.0/Standard/max10-jtag-secure-unlock/

Let me know your concern.

Thanks.

Regards,

Aiman

[DamBam]

Hi @NurAiman_M_Intel ,

Thank you for response.

Yes, I followed the instructions in the document, and the design worked as described in the document, I was able to run JAM file in quartus_jli. I observed that FPGA reconfigured when JTAG was unlocked, and didn't reconfigured when JTAG is locked.

But then, after triggering unlock (by pressing pushbutton), in Quartus Programmer (connected to JTAG I/O) I couldn't program a new SOF file to CRAM nor new POF to on-chip flash. I couldn't erase on-chip flash as well untill the power cycle is performed on the board.

After power cycle, and triggering unlock command (PB), I was able to program SOF, POF and erase.

I run this exmaple on terasIC DE10-Lite, the simulation was performed before hardware run, because I didn't wat to lock the devboard permanently.

Thanks, and looking forward to hear from you

DB

[NurAiman_M_Intel]

Hi,

Please check if the design that you used has the unlock function.

The reason is that based on the testing, I understand that the design in the flash does have this function where after you power cycle and the Max 10 device is loaded with JTAG Secure design and JTAG unlock function then you were able to unlock the device successfully.

If you are using the incorrect design then you will face issue on unlocking the JTAG chain and will cause JTAG programming to fail.

Thanks.

Regards,

Aiman

[VecFPGA]

Hi everyone,

I’m also having problems with the lock/unlock instruction in the mentioned example. The issue is that after programming the FPGA (on the MAX10 Development Kit) with the design example (in question), the following happens:

1. When I activate the JTAG_LOCK command (with a button), I can still access the JTAG chain without any problems.
2. The CONF_DONE pin is always high (even though it returns a different error, see below).
3. I cannot program the .pof/.sof files, erase or verify, and I get the following messages:

• Error (209012): Operation failed,
• Error (209014): CONF_DONE pin failed to go high in device 1. Make sure all communication cables are securely connected, select a different device, check the power on the target system, or make sure all nCE pins are connected to GND...

If I try to erase CFM0 or UFM individually, it says that the operation was successful, but that’s not the case because the application is still running on the FPGA.

I hope to get some feedback or ideas from you about this.

Thanks in advance.