MAX10 RAM (M9K) content at power up?

[Altera_Forum]

I am using MAX10 10M04DCF256. 

 Documentation for the M9K RAM blocks makes clear that the output register of the RAM is cleared at power-up and you don't see RAM content at the output until after the first read cycle.  The tools also provide for specifying the RAM content as part of the configuration data - but not on the 'DCF' devices as the flash is too small for a configuration image with RAM initialisation.  I was therefore expecting that RAMs in my design would power-up with arbitrary content.  However, on my prototypes I am finding that the RAM is in fact cleared to zero at power-up.  Is this a fluke, or is it an undocumented feature that a configuration file without RAM initialisation actually initialises it to zeros?

[Altera_Forum]

All FPGA registers, including those in a RAM block unless initialized with a .hex or .mif file, power up low. This is common across all device families (though Stratix 10 does now allow you to power up a register to 1).

[Altera_Forum]

Thanks. I guess you mean "All altera FPGA families" as it's definitely not the case elsewhere!