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MAX10 flash memory address mapping

Altera_Forum
Honored Contributor I
1,016 Views

Hi, 

 

 

I have instantiated an Altera on chip flash memory in a code to perform field upgrade in a 10M08 device.  

1. Please clarify the starting address to be used, to write an application image to CFM1 & CFM2. 

2. Why is the address line width is [16:0] (in fig.2), and not [17:0] even though it require 18-bits to represent the address space of CFM1 & CFM2. 

 

 

 

https://mail.google.com/mail/u/1/?ui=2&ik=977f7fa26c&view=fimg&th=15b8a3972cb8686e&attid=0.1&disp=em...  

 

fig.1 - Address Mapping in Dual Compressed Image configuration mode 

 

 

https://mail.google.com/mail/u/1/?ui=2&ik=977f7fa26c&view=fimg&th=15b8a40e7fc9038c&attid=0.1&disp=em...  

 

fig.2 - On Chip Flash IP  

 

 

Thanks in advance , 

SSK
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
77 Views

I think the flash ip is using word address (32 bit), not byte address. 

 

 

--- Quote Start ---  

Hi, 

 

 

I have instantiated an Altera on chip flash memory in a code to perform field upgrade in a 10M08 device.  

1. Please clarify the starting address to be used, to write an application image to CFM1 & CFM2. 

2. Why is the address line width is [16:0] (in fig.2), and not [17:0] even though it require 18-bits to represent the address space of CFM1 & CFM2. 

 

 

 

https://mail.google.com/mail/u/1/?ui=2&ik=977f7fa26c&view=fimg&th=15b8a3972cb8686e&attid=0.1&disp=em...  

 

fig.1 - Address Mapping in Dual Compressed Image configuration mode 

 

 

https://mail.google.com/mail/u/1/?ui=2&ik=977f7fa26c&view=fimg&th=15b8a40e7fc9038c&attid=0.1&disp=em...  

 

fig.2 - On Chip Flash IP  

 

 

Thanks in advance , 

SSK 

--- Quote End ---  

Altera_Forum
Honored Contributor I
77 Views

Have you solved this Issue I am running into the same problem. I am assuming that I can just drop the lower 2 bits but I want to make sure.

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