Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20402 Discussions

MAX10 linker NIOS/e program to external Hyper RAM?


I have done a Hyper RAM controller by systemverilog and communicate to it due to "mm_pipeline_bridge" in QSYS. I can write and read data into my external Hyper RAM under NIOS program. Everything work correctly while accessing as data due to BASE_ADDRESS generated by QSYS.  But now  I want to put my code into external Hyper RAM and gotten failure. In Linker I composed a memory device an regions with appropriate addresses (QSYS), after that I have chosen in linker ( .bss, .heap, .stack, .rodata, .rwdata, .text) tab of bsp editor and set composed regions. Everything is compiled. No errors. And all .hex files generated (on_chip_flash.hex, mm_bridge_0.hex and on_memory_0.hex). After that I have generated a .pof file and chosen option "load memory file" with "on_chip_flash.hex".

What changes do I have to make in linker script for that? 

0 Kudos
0 Replies