We had an external ADC connected to a MAX10 (10M50). To investigate the signal integrity of the signals between the MAX10 and ADC, eye diagrams of various signals were recorded. We noticed a bit strange behavior with the output driver of the MAX10.
The output signal (output strength set to LVCMOS 2mA) of the MAX10 is shown in the picture TC73_02_ADC_clock_amp_1_2.png. What we noticed are the levels in the output signal of the MAX10. Whereas the output signal of the external ADC (picture TC73_02_ADC_SDOA_amp_1_2.png) looks as expected.
Is there an explanation for these levels in the output signal (rising and falling edge) of the MAX10 driver
I am little confused on the query here. You said, an external ADC was connected to MAX 10. So, ADC output is becomes an input to MAX 10, right? Are you checking at the MAX 10 input pin?
Sorry for my imprecise wording.
The picture "TC73_02_ADC_clock_amp_1_2.png" shows an output of the MAX10, here the clock signal to the ADC (input signal for ADC), with the mentioned levels in the signal curve.
For comparison, "TC73_02_ADC_SDOA_amp_1_2.png" shows the output signal of the ADC (input signal for MAX10), which has no levels in the output signals.
These levels in the output of the MAX10 have been observed on many of the recorded eye diagrams.
Looks like this thread was left unattended. Sorry about that. Not sure, if you still need the support, but putting my thoughts here.
As the output is LVCMOS, there could be a chance that the signal strength is not enough. You can try increasing the strength.
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