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Beginner
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MAX10 using external PLL with soft-lvds gives always a warning: Warning (15064): PLL... jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

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the LVDS signals are connected to a tft display. The picture is ok so far only, but after each comilation and program the fpga with more or less jitter.

Compilation give the warning:

Warning (15064): PLL mypll:mypll|altpll:altpll_component|mypll_altpll:auto_generated|pll1" output port clk[3] feeds output pin "LVDS_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

 

Pll-c0(1:1): tx-syncclock

Pll-c1(7/2): tx-inclock

Pll-c3(1:1): LCDS-clockpins

I can not see an other way to feed the LVDS-Clock output with the 1:1 clk as to connect directly.

If I use the Soft-LVDS with internal PLL it will not work (no picture on the tft-display).

I am interesting in how the Soft-LVDS will do the work internal if the pll is inside the macro.

Thank you.

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Employee
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Hi @SZand​ 

 

Let me sum it up. There are 2 issues

1) warning on non-dedicated output clock

2) sdc constraint output paths

 

For (2), you might want to put on a new thread and refer to this thread so that my colleague could take detail look into your case.

 

For (1), Pll-c3(1:1): LVDS-clockpins which was supposedly your tx_outclock, should be connected to dedicated PLL clock output pin (e.g. PLL_L_CLKOUTp). Example pin 32/33.

50/52 is not a dedicated PLL clock output pin (e.g. PLL_L_CLKOUTp). Thus the warning.

There isnt any sdc constraint that can dismiss the warning.

 

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3 Replies
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Employee
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Hi @SZand​ 

 

I created a simple design with a MAX10 device. Inside this simple design there are:

1) SERDES block with Internal PLL

2) SERDES block with external PLL

 

I dont see the warning in either one.

I attached the QAR.

 

Meanwhile could you check if your clock out pin is connected to a dedicated PLL clock output pin (e.g. PLL_L_CLKOUTp)?

 

if you are still facing problem, could you send me a simple design that shows the warning?

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Beginner
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Hi JwChin,

thank you for your answer.

No, the the LVDS-Clock (as 1:1 clock from the pll) is connected to pins 50/52 (10M16SAE144).

The jitter problem seen on the display is solved (timing problem of the input latch not inside the SOFT-LVDS), but the above warning is still there. There are also other warnings from Timequest regarding not constraint output paths (all LVDSp/n pin paths).

I am interested in getting less as possible warnings. Probably there are settings in the sdc file that can be used to tell Quartus / Timequest that all is ok.

Best regards.

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Highlighted
Employee
35 Views

Hi @SZand​ 

 

Let me sum it up. There are 2 issues

1) warning on non-dedicated output clock

2) sdc constraint output paths

 

For (2), you might want to put on a new thread and refer to this thread so that my colleague could take detail look into your case.

 

For (1), Pll-c3(1:1): LVDS-clockpins which was supposedly your tx_outclock, should be connected to dedicated PLL clock output pin (e.g. PLL_L_CLKOUTp). Example pin 32/33.

50/52 is not a dedicated PLL clock output pin (e.g. PLL_L_CLKOUTp). Thus the warning.

There isnt any sdc constraint that can dismiss the warning.

 

View solution in original post

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