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Max 10 - adc output stacked low

Altera_Forum
Honored Contributor II
‎06-30-2017 01:51 PM
1,037 Views

Hello friends!  

I'm starting with altera fpga, in particular I am using MAX 10 series and quartus prime lite (17).  

Since I trying to create an ADC in a 10M08SAE144.. fpga and compilation summary reports that no logic depend on input clock that I used and that all pin connected to the adc data out are stacked low, I considered the idea to download some adc example, as the one below: 

 

https://cloud.altera.com/devstore/platform/16.0.0/standard/adc-and-audio-monitor/ 

 

When I open these examples after compilation I get the also same warning (please see attached picture) 

 

Somebody can give me some example that use ADC exporting converted digital data to output IO pins? 

 

Since my english is not so good :wacko::wacko::wacko: I hope you will understand my problem and you'll help me:).. 

 

Thanks in advance for your help,  

 

Regards!
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PRiva1
Beginner
‎07-05-2019 10:58 PM
325 Views

Did you ever solve this?

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