Max 10

[Altera_Forum]

Hello! 

 Does anyone know when will altera provide support for MAX 10 SA series FPGA? I cant find any BSDL file, package dimmension, early power estimator and many more. Why did they release device without support?

[Altera_Forum]

Also i would like to know where did they found 101 IO pins. Ive found just 100 IO pins in version 10M08SAE144C8GES. Which pins are used for suplying core because in pin-out list are marked as VCC_ONE.

[Altera_Forum]

Hi. 

wasn't the support for MAX10 FPGA added with the update to QII 14.0 available for download at altera.com? Besides this all alreday provided like datasheet, pinout, ... is listed at MAX10 device section on altera.com, try http://www.altera.com/literature/lit-max-10.jsp :-) The VCC_ONE option is listed in the pin connection guidelines as an option to connect all VCC Pins (I/O and core) to 3.3V and use an internal 1.2V core voltage regulator to minimize the external device count. Besides this option you can still connect I/O and core separately as also defined in the PCG.

[Altera_Forum]

Aaaand one more question :) is there any way to configure this FPGA? i dont want to use JTAG because i want to program this IC in device and there is not acceptable to program each device separately.  

 Many thanks!

[Altera_Forum]

According to the documentation referenced, the MAX10 provides a JTAG I/F to access the internal configuration ROM. As JTAG can be cascaded, you can put more than one device on the Chain to configure these. Ok - this serializes the programming, thus you cannot Programm more than one MAX10's Flash at the same time (but this is not different to the active Serial programming of Config.-EEPROM like e.g. for Cyclone IV etc., is it?)

[Altera_Forum]

Yes but i need to configure it like passive serial. So this device dont have real enforcement in serial production. Should be fine if engineers from Altera engage in conversation.

[Altera_Forum]

Maybe I'm blind eyed to miss the point - I would agree that passive serial is an option for systems with e.g. an µC that configures the FPGA on power up to eliminate the requirement for a separate configuration ROM. For the MAX10 the configuration Flash is built-in, thus the MAX10 configures without an external ROM. This internal ROM needs to be programmed once in production, e.g. at the same time the board assembly is tested by using the JTAG I/F already... 

What would be the benefit to program the internal ROM by passive serial I/F rather JTAG?

[Altera_Forum]

What is the biggest advantage of FPGA ? Reconfiguration. And i need it reconfigure it many times in circuit. And if i will produce 1000 pcb-s with this device i dont want to program each one!

[Altera_Forum]

Ok - if you intend to reconfigure the FPGA in system many times (e.g. during system operation) rather programming the assembled FPGA during electronics final assembly and perhaps on system upgrade (respectively by remote update) the MAX10 might be the wrong device. Just to be sure - the MAX10 is programmable on board - not like the frist GAL/PAL devices that had to be programmed with programming Hardware prior being assembled. Maybe this is best compared with the JTAG loader Option as provided by the Cyclone family :-) 

I use FPGA on board with different configuration files to use the same Hardware in different applications - these boards are assembled completely with "dumb" FPGA (resp. empty config EEPROM) and the program is loaded with as a final step in system assembly. But with the programmed board installed in the target application there is no further updates / change of configuration in operation...

[Altera_Forum]

--- Quote Start ---  What is the biggest advantage of FPGA ? Reconfiguration. And i need it reconfigure it many times in circuit. And if i will produce 1000 pcb-s with this device i dont want to program each one!  --- Quote End ---   You should use sof file for directly configuration of the MAX 10 logic array via JTAG (not for CFM programming, for CFM programming you must use pof file). After the power is switched off your configuration will be lost. This will be an "analogue" of the passive serial configuration, as you want. Is not it?