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Max II CPLD configuration question

Altera_Forum
Honored Contributor II
‎01-10-2009 06:47 PM
1,190 Views

I'm new to CPLD and now I am reading Max II CPLD document. Here is my question: 

 

After CPLD is programed, the CPLD is powered down and then powered up. How is the configuration updated from flash? Does it need a clock running to do the configuration or the configuration is totally static without any clock needed. 

 

Thanks in advance.
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Altera_Forum
Honored Contributor II
‎01-11-2009 08:44 AM
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CPLD configuration circuitry is non-volatile(based on EPROM or EEPROM or fuse or antifuse), program is not lost on power down. Once configured thats it. You don't need flash or any external memory for that. 

 

Most FPGA configuration circuitry based on SRAM and are volatile
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