Megafunction altparallel_flash_loader--what is this

[Altera_Forum]

Hi All 

 The flash loader in the megawizard, for the cyclone III will that let me write and read bytes the the Flash. If so is there any information in its setting etc.  I have been struggling making a state machine that can save and read data in flash mem, could this be a soloutions Pleae do let me know

[Altera_Forum]

I believe the parallel flash loader is a megafunction that will configure your fpga from a CPLD/FLASH combo, and also allow flash programming via jtag. 

 I dont think the it is the solution to read and write flash memory from an fpga.

[Altera_Forum]

How about using the Common Flash Interface Controller core in SOPC builder? (http://www.altera.com/literature/hb/nios2/n2cpu_nii5v3_01.pdf) Then you can add a simple SM as your avalon master to access the flash.

[Altera_Forum]

Can SOPC builder work for me as Djoshi says? I need flash to store a datasheet. 

First, I write it , then FPGA reads the datasheet out. Problem is that how I can write the datasheet which contains all displacements into the flash. I have read some books about NIOS2 , most of which tell me how to configure the fpga via the flash, but less examples about storage used in them. Could you explain it more ? Better a step to step way. Thanks very much!

[Altera_Forum]

Can you describe what format is the data sheet in? How do you plan to get the data into the FPGA?

[Altera_Forum]

The data sheet I use is 512K , which contains address and data as the picture I attached. 

The data sheet was made with VC++, the format boss gave to me is " .DAT" , you can open it in UltraEdit. I plan to use jtag to download the data sheet into FPGA , then the FPGA write the data into the flash. Problem is I don't know whether the Flash Programmer of Nios IDE can get it. The data written into the Flash will be read by FPGA , meanwhile FPGA works. I had used MCU to write W29C040 and DS1250Y-70. It is the first time I use Nios , the materials I get from altera is just using Flash to configure the FPGA but not to store data as I said. That is my trouble bothering me for a long time. Look forward to your reply! Thanks very much.

[Altera_Forum]

Hapyang, 

 From what I can tell, your data sheet does not contain address info; the address info is provided by UltraEdit as it displays the contend of your binary file.  If you are building an independent system, you would need add a JTAG UART, Nios II, and a Common Flash Interface Controller core to your SOPC builder. Write some code for Nios to read from the JTAG UART and write to the Flash controller. You will need to decide the starting address you want to write in the flash and increment the address as you write.  Having said the above, Altera has already included a Nios II Flash Programmer which does this. (http://www.altera.com/literature/ug/ug_nios2_flash_programmer.pdf) Instead of using a JTAG UART and writing your own code, Nios II Flash Programmer transfer the data via Nios' JTAG debug port.  Hope this helps.

[Altera_Forum]

Thanks very much , Ychen. 

It is greatly helpful to me . I am printing the PCB now , the flash was bothering me ,because I use Quartus , never use Nios2 before ,so I don't know whether it works. Now, I can go on my work. Thanks again.  Any problems I can't deal with , I 'll ask for your help again.;)

[Altera_Forum]

In my work, I plan to use two flash to store the data sheet, which are two seperate data sheet. In the same clock cycle, FPGA can get the two flash data. Actually speaking, the data sheet are all 16bit data-width , so with two 16bit data-width flash , I can get 32 bit data-width at the same time. 

When I add "cfi_flash_0" and "cfi_flash_1" into SOPC ,both of them link to "tristate_master" , then can I control the two flash seperately when I write them and read them at the same time ? they all link to "tristate_master" ! Hope for your reply! Thanks very much!

[Altera_Forum]

I think there are multiple issues here. First of all, the flash might be configured with dynamic bus sizing which means that a single access from Nios which is 32-bit will translate to two 16-bit operations over multiple cycles. Secondly, with a single master such as a single Nios, you can either read or write a slave but not both at the same time. Hence, it is impossible to control two flash seperately at the same time unless you have more than one master (and multiple tristate_master). 

 Do you really need to access both flash at the same time?

[Altera_Forum]

Thanks very much, ychen. 

In my work , I want to use two data sheets , which are two related sheets, one is displacement, the other is related PWM signal that will drive other circuits. I have to give FPGA the the two 16bits-width-data at the same time. I don't know any better ways to give FPGA 32 bits-width data except accessing both flash. I will be very grateful to you If you could advise me some better ways. I tried to use two Tri-state bridge and two CFI in the sopc design, and link the first Tri-state bridge to CFI0, the second one to CFI 1, then I generate the sopc.bdf. It seems like it can work. Shown as the pic I attached.

[Altera_Forum]

If you are always accessing the 16-bit displacement and 16-bit PWM pari at the same time, you might want to combine the flash and make them appear to be a 32-bit flash and treat your data as 32-bit. It is possible to make both flash completely independent, with separate tri-state bridges as described, but this means you also need to have separate address & data for each flash which will consume lots of IO pins. You will also need to have another master to take advantage of simultanenous access to both flash. 

 Depending on the data type defined, Nios will adjust the access accordingly. For example, if you define a 32-bit word in Nios and when it is written to a 16-bit flash, I believe Nios will write to two consecutive locations. http://www.altera.com/literature/hb/qts/qts_qii54003.pdf