Memory Test fails whith 256-MB DDR2

[Altera_Forum]

When using the SDRAM DDR2 with 64-bit data bus width, the memtest fails! And the failure occurs only in specific locations (spans of 0x10): 

  --- Quote Start ---   ERROR: DDR2 was not filled up properly at location (0h) ERROR: DDR2 was not filled up properly at location (10h) ERROR: DDR2 was not filled up properly at location (20h) ERROR: DDR2 was not filled up properly at location (30h) ERROR: DDR2 was not filled up properly at location (40h) ERROR: DDR2 was not filled up properly at location (50h) ERROR: DDR2 was not filled up properly at location (60h) ERROR: DDR2 was not filled up properly at location (70h) ERROR: DDR2 was not filled up properly at location (80h) ERROR: DDR2 was not filled up properly at location (90h) . . . .   --- Quote End ---  While dealing with less data bus width returns with no failure. I am using the Cyclone II DSP development kit, and I took the standard design as a starting point and just modified the data bus width of in the SDRAM controller. Am I having timing problem? If anyone can tell me what is the problem I will be appreciated.  thx

[Altera_Forum]

Are you using Nios II and the memtest software or your own custom method? Also what is the data width and burst lengths set to for both the SDRAM controller and the master performing the read/write accesses?

[Altera_Forum]

well I am using both methods and both failed. I just made a custom program to check where the failure is located. Anyway, the data width as I mentioned is 64 bit and the burst length is 4 for the SDRAM controller, I just took the STANDARD design and modified the data bus width to 64. I am using a read master by a SG-DMA (with 3 bit burstcount signal width), and a write master by the Nios II processor data master.

[Altera_Forum]

Have you tried a walking ones pattern with bursting disabled? If you find that passes but your burst test does not let me know and I'll point you at some text for a bug I wrote not too long ago (it's not up on the web yet....)

[Altera_Forum]

Also search for "Board Bring-up" in this document if you are not familiar with the tests I'm referring to: http://www.altera.com/literature/hb/nios2/edh_ed51010.pdf

[Altera_Forum]

Okay,  

I disabled bursting but still have the same problem. The 'walking ones' test failed at the same address (as when bursting is enabled) which is 0x10000.

[Altera_Forum]

I seem to recall that the design uses a reduced number of row addresses to reduce the SDRAM span (it's too large to hook up to the Nios II instruction master). That memory device should have it's own presets so you may want to go into the SDRAM controller and re-apply the preset to make sure the parameterization is correct.

[Altera_Forum]

It seems that the the parametrization is correct!