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Multi SD CARD controller

Altera_Forum
Honored Contributor II
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Hi all,  

I'm doing a design with 4 SD cards, in sd 4 bits mode at 50MHz in parallel with an embedded Nios on a ARRIA V target.  

 

Here are the facts:  

- By instantiating the sd ip without Nios, communication goes well and we arrive to write fixed pattern on all cards.  

- By adding the Nios (Nios + RAM + Ethernet), there are 2 cards of 4 arriving to work properly  

 

Has anyone ever used multiple SD cards within one design?  

 

Are there timing constraints add on the sdc file to use efficiently sd card ?  

 

I suspected problem of random delay depending on the quartus routing or fitting, between the sd clock and the 4 bits of data. 

 

Thank you for your help
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Altera_Forum
Honored Contributor II
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How have you constrained this? 

 

Yes, you will have to ensure you clock to out times are appropriate. However, you mention running at 50MHz - I don' think you should have much of a problem in Arria running at that frequency. 

 

Are you registering data on and off the FPGA in the I/O cell? 

 

Are you happy that, in connecting up your Nios core, you haven't inadvertently incorrectly connected something? 

 

Regards, 

Alex
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Altera_Forum
Honored Contributor II
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Hi Alex 

 

Thank you for responding, 

 

Yes, data are registered in the I/O cell. 

I'have checked, all connections are ok. 

 

Below the corresponding sdc file lines and attached the sd specification, could you check if it is correct? 

 

#create 50 mhz clock 

create_clock -period 20 -name {c0_sd_clk} [get_ports {c0_sd_clk}] 

 

# constraint of sd output delay time (fpga input) 

set_input_delay -clock { c0_sd_clk } -add_delay 14 [get_ports {c0_sd_dat* c0_sd_cmd}] 

# constraint of sd output hold time (fpga input) 

set_input_delay -clock c0_sd_clk -min -rise 2.5 [get_ports c0_sd_dat* c0_sd_cmd] 

 

# constraint of sd input setup time (fpga output) 

set_output_delay -clock c0_sd_clk -max -rise 6 [get_ports c0_sd_dat* c0_sd_cmd] 

# constraint of sd input hold time (fpga output) 

set_output_delay -clock c0_sd_clk -min -rise 2 [get_ports c0_sd_dat* c0_sd_cmd] 

 

Regards, 

Hery
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Altera_Forum
Honored Contributor II
960 Views

the SD SPECs bus timing paragraph

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Altera_Forum
Honored Contributor II
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Are you still having problems with this? 

 

I don't see anything wrong with the set of constraints you've posted. Can I assume you used this same set of constraints successfully in your non-Nios version? 

 

My suspicion her is still with a higher level functional issue. 

 

Regards, 

Alex
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Altera_Forum
Honored Contributor II
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Hi Alex, 

 

Thanks for your help. 

Timing constraints and data synchronisations were failed. 

 

Regards, 

Hery
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