NCO help...

[Altera_Forum]

Hi i'm trying to test a fixed point filter on a FPGA board, my filter has an input of 16 bit, but the maximum value it can take without saturation is 1023 which is 11 bits. so far the only signal i've been using to is the NCO megafunction. when i set the NCO to have a magnitude of 16 bits i get severe distortion and loss of precision, i cant change the NCO to have a smaller number of bits or i get a bit mismatch, and i cant reduce the number of bits of the filter because i get distortion and loss of precision again. i'm using simulink and fixed point advisor in simulink to design this filter.... 

 Can anyone please help..? not sure if there is another way to test the filter with a more dynamic signal. or if anyone is familiar with simulink how i can optimize my design.

[Altera_Forum]

A short cut is to set NCO to 10 bits then sign extend its output to16 bits

[Altera_Forum]

How do you do sign extension?

[Altera_Forum]

If you are working on schematics then just connect MSB of NCO to all remaing MSBs of filter input. 

 if you want VHDL then:  sine16 = std_logic_vector(resize(signed(sine11),16));  You can also keep your NCO on 16 bits then select its 11 MSBs instead of setting it to 11 bits., your choice ...

[Altera_Forum]

And the other option is to rescale your coeffs so that you get unity gain, set their sum to 2^15 ( or 1.0 normalised)

[Altera_Forum]

--- Quote Start ---  If you are working on schematics then just connect MSB of NCO to all remaing MSBs of filter input.  if you want VHDL then:  sine16 = std_logic_vector(resize(signed(sine11),16));  You can also keep your NCO on 16 bits then select its 11 MSBs instead of setting it to 11 bits., your choice ...  --- Quote End ---    Wouldnt this give me a width mismatch? because i'm not sure exactly how i would do this can i get an example...i'm talking about schematic way.

[Altera_Forum]

If you have say A = 8 bits signed and you connect it to B = 12 bits signed then you connect 8 LSBs of A to 8 LSBs of B. 

But the remaining 4 MSBs of B must not be zeroed, but must follow sign bit of A.  e.g. 0000 1111 = + 15 on 8 bits 0000 0000 1111 = +15 on 12 bits  1111 0001 = - 15 on 8 bits 1111 1111 0001 = -15 on 12 bits  Hope it is clear.

[Altera_Forum]

Yes i do understand that, but not that brings up a good point...since the NCO is a sinosuid it'll have negative and positive values...how would i accomodate for that?

[Altera_Forum]

If your NCO is swinging +/- 1023 on 11 bits then it will swing +/- 1023 on 16 bits provided you connect as described.

[Altera_Forum]

I still cant seem to figure out to match them on the schematic....this is what i was referring to.

[Altera_Forum]

Assuming both data are 2s complement (NCO output definitely is), just copy bit 10 to bit 11. You need to access individual bits for this. It's only a trivial schematic entry problem, not related to DSP or NCO anyhow. The standard library has e.g. a wire component to connect different nets.

[Altera_Forum]

sorry i'm fairly new to quartus and i'm not familiar with doing this...so how exactly do this...or i should say what component do i use.

[Altera_Forum]

The name of the component is exactly "wire".

[Altera_Forum]

--- Quote Start ---  The name of the component is exactly "wire".  --- Quote End ---   But the wire doesnt give me the option to do what you are describing. i feel like we're talking about two diffeerent things here.

[Altera_Forum]

To further Clarify what i'm saying is, i have an NCO with a 11bit output. but the filter has a 12 bit input. under these conditions if i just simply draw a wire i will get a width mismatch. i tried to do this in VHDL like Kaz suggested but it wouldnt work. if it's easier to do it in the schematic i would prefer that way. i just want clear detailed instruction as i have never done this before and information online seems scarce.

[Altera_Forum]

Okay i see...so what happens to the last bit on the 12 bit input?

[Altera_Forum]

--- Quote Start ---  See below two simple methods to achieve what you want. There are more (including more elegant) methods described in the online help under using connectors.  Try and have fun!  --- Quote End ---    Great! it finally works! but quick question..? so does it connect to the MSBs of the input port or the LSBs of the input port.

[Altera_Forum]

It should be seen as a sign extension example, driving the unused MSB lines with the sign bit, it's under the sassumption, that the imput signal is signed in 2s complement.

[Altera_Forum]

Okay another problem, when i do it as you described the input signal swings between 1023 and -2042 when it should be swinging from 1023 to -1024. This is causing severe saturation. so how do i make it so it stays within the range of an 11 bits. i'm assuming the way to do this would be to use the 11 LSB instead of the 11 MSB. If you look at my attached document you can see that the bus line is only 11 bits i'm not even sure how its possible for the bus line to have a value passed 1023, the only thing i can think of is that it's not being treated as a signed number. please help.

[Altera_Forum]

Are you displaying values correctly? I think you have set it to sign and magnitude instead of 2's complement since the sine values suddenly dip max negative after positive section.

[Altera_Forum]

Yes i am showing sign and magnitude, but regardless the magnitude shouldnt be even close to that value.