Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Native PHY - Bitslip latency




I'm using the Native PHY with 2 Arria V FPGAs.

One FPGA has the transceiver implemented as Tx only and the other as Rx only.

In simulation - I send a predetermined word on from the Tx FPGA - for example: 0x4A64 and monitor the received data on the Rx FPGA.


The Rx FPGA receives the word unaligned - so I must assert the PHY's Bitslip signal a number of times until it's aligned.

This works - but one thing bothers me...I noticed that there's a 10 clock latency between Bitslip assertion and data shift actually occurring.


This doesn't match the behavior of the PHY as it's described in the documentation:

As you can see - here the data is shifted immediately with the assertion of the Bitslip signal.


Why my simulation doesn't match the behavior in the documentation ?  

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As I understand it, you have some inquiries related to the AV bit slip behavior in simulation. You seems to observe that there are ~ 10 clock cycle latencies from the bitslip assertion to the RX parallel data output change.


Based on my understanding on the AV XCVR channel PCS blocks, from word aligner (bitslip mode) to rx_parallel_data output, there are a number of PCS blocks ie rate match FIFO, 8b10b, byte deserializer, byte ordering and phase comp FIFO. Therefore, there will be latency from  when you apply bitslip to when the data is observed at the rx_parallel_data output ports.


I believe the Figure 38. RX Bitslip in 16-bit Mode is just to show the high level concept of how bitslip would function.


Thus, I would recommend to refer to the functional simulation which would mimic the actual hardware behavior.


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin