Kindly check the 'MAX 10 FPGA Device Datasheet' link below on - Page 26 (Table 27)
Thanks a lot.
It says in the note "This parameter is limited in the Intel Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard."
Do I have to compile the hole design to be able to see this or is there some other way?
I'm designing the hardware now and want to make sure that the device can handle the input frequency before starting to compile/program fpga.
Yes - you should consider compiling a representative design before completing any hardware. Using Quartus allows you to both confirm pinouts and helps you with timing issues.
You mention input frequency. Modern FPGAs, inclucing MAX 10, have PLLs allowing you to configure the speed at which the logic is clocked. Providing you chose a sensible input frequency for your source clock you will be able to retain a great deal of flexibility through the FPGA design. Failing that it's usually not hard to find a clock source, in the same package, with a different frequency...