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Honored Contributor I
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Need help using transceivers on Stratix II Gx with alt2gxb megafunction

Hey everyone, 

 

I am trying to get a very simple design to work: I have a 16-Bit counter and want to send and receive the 16 Bit number via the transmitter and receiver of the same channel. 

I found a thread in this Forum for exactly the same project, but there was not enough information for me and the most recent post in it was from 2009. 

 

In the best case I would like to have working example files if anyone could provide them. 

But Tips or directions to a good tutorial would also be highly appreciated. 

 

So let me tell you what i did up till now: 

The Parameters of the alt2gxb in the most recent version of my project look like this: 

Basic Protocol, no loopback 

Receiver and Transmitter, one channel, width: 16 Bit 

 

frequency 100 MHz data rate 1000 (maybe this is one of my problems, but low datarate shouldn't be problem, should it? The post i was referring to said that you ought to use the sfp_refclk with 155.56 MHz. I tried it, but then the project wouldn't compile because somehow it wouldn't accept any standard (LVDS or otherwise) in the pinplanner so now I simply use what is called "CLK 1"). 

 

I train the receiveer PLL from pll inclk 

 

For Reset I use gxb powerdown, rx digital, rx analogue tx digital, pll locked and rx freqlocked with an initialization sequence like advised in the Stratix II gx transceiver architecture overview on page 217. 

 

On the Ports/callibration page i just checked "use calibration block" and connected the resulting input with my 100 MHz clock 

 

8b/10b encoding is enabled and word alignment is manual (I don't really use word alignment, I know that I should, but i was under the impression, that for the first few numbers sent after the initialization sequence there shouldn't be alignment issues? Is that kind of thinking wrong?). 

 

The initialization sequence that i mentioned above starts when I push a button on the dev board. 

This way I can programm the FPGA via signaltap, start data aquisition and THEN get the design going (so I really se the very first events on the output of my transceiver). 

I record the rx_out_wires of the alt2gxb function, what comes out looks like what i attached. There are a lot of FEFEs (i guess they are some kind of controll signals, but they are not the standard word alignment pattern) and the data that is not FE is just random and doesn't look like a counter to me. 

 

So yeah thats it, any help would be appreciated. 

 

Thanks a lot in advance. 

Cheers
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