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Altera_Forum
Honored Contributor I
775 Views

Negative Hold slack with NIOS II in MAX10

Hi everyone! 

 

I'm trying to execute NIOS's code from User Flash Memory located inside MAX10. 

My eval board is https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-max-10-evaluation.html

 

Onboard clock 50 MHz I connect to NIOS clk input. 

In top-level .sdc file I create this clock by string: create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports { clk }] 

 

But after Quartus processing, Timquest find negative hold slacks for all drdout[] nodes of UFM block. 

I see that Timequest analyze path from each drdout[] node to itself! 

I don't understand what is the sense of it ? 

 

Moreover, after deleting string "create_clock -name {clk} -period 20.000 -waveform { 0.000 10.000 } [get_ports { clk }]" from top-level .sdc file everything is OK, i.e. Timequest doesn't find negative slacks. 

But I think, it's wrong idea to delete "create_clock..." from sdc file. 

 

Who can help to define problem ?
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Altera_Forum
Honored Contributor I
39 Views

The problem is in Quartus version 15.1. 

Compiling the same project in Quartus v16.0 doesn't detect problem with timing.
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